Exascale Computing: More and Moore?
Hedco Auditorium (SGM 123)
Lecture: 4:30 to 5:30 PM
Reception: 5:30 to 6:30 PM
With petascale systems becoming broadly available in high end computing, attention is now focused on the challenges associated with the next major performance milestone: exascale computing. Demand for computational capability grows unabated, with areas of national and commercial interest including global climate change, alternative energy sources, defense and medicine, as well as basic science. Past growth in the high end has relied on a combination of faster clock speeds and larger systems, but the clock speed benefits of Moore’s Law have ended, and 200-cabinet petascale machines are near a practical limit. Future system designs will instead be constrained by power density and total system power demand, resulting in radically different architectures. The challenges associated with exascale computing will require broad research activities across computer science, including the development of new algorithms, programming models, system software and computer architecture. While these problems are most evident at the high end, they limit the growth in computing performance across scales, from hand-held client devices to personal clusters and computational clouds.
In future computing systems, performance and energy optimization will be the combined responsibility of hardware and software developers. Since data movement dominates energy use in a computing system, minimizing the movement of data throughout the memory and communication fabric are essential. In this talk I will describe some of the open problems in programming models and algorithms design and promising approaches used so far. These will build on the ideas of Partitioned Global Address Space languages and Communication Avoiding algorithms, but extended to more complex memory hierarchies. In addition to these universal problems, fault resilience is a problem at the high end that will require novel system support, possibly propagating up the software stack to user level software and algorithms. Overall, the trends in hardware demand that the community undertake a broad set of research activities to sustain the growth in computing performance that users have come to expect.
Kathy Yelick is the Associate Laboratory Director for Computing Sciences and the Director of the National Energy Research Scientific Computing Center (NERSC) at Lawrence Berkeley National Laboratory (LBNL). She is also a Professor of Electrical Engineering and Computer Sciences at the University of California at Berkeley. She is the author or co-author of two books and more than 100 refereed technical papers on parallel languages, compilers, algorithms, libraries, architecture, and storage. She co-invented the UPC and Titanium languages and she co-developed techniques for self-tuning numerical libraries, including the first self-tuned library for sparse matrix kernels. Her work includes performance analysis and modeling as well as optimization techniques for memory hierarchies, multicore processors, communication libraries, and processor accelerators. She earned her Ph.D. in EECS from MIT and has been a professor at UC Berkeley since 1991 with a joint appointment at LBNL since 1996.
Published on September 27th, 2016
Last updated on February 10th, 2017