Technical Reports
| CENG-2017-01 | SPORT Lab SFQ Logic Circuit Benchmark Suite by Navven Katam, Soheil Nazar Shahsavani, Ting-Ru Lin, Ghasem Pasandi, Alireza Shafaei, and Massoud Pedram |
| CENG-2017-03 | Optimizing Frequency Domain Implementation of CNNs on FPGAs Hanqing Zeng, Ren Chen, Viktor K. Prasanna |
| CENG-2015-10 | High Throughput Large Scale Sorting on a CPU-FPGA Heterogeneous Platform by Chi Zhang, Ren Chen and Viktor Prasanna |
| CENG-2015-11 | Accerlerating Equi-Join on a CPU-FPGA Herterogeneous Platform by Ren Chen and Viktor Prasanna |
| CENG-2016-01 | Static LQG team with convex function by Seyed Mohammad Asghari and Ashutosh Nayyar |
| CENG-2016-02 | Centralized Minimax Control by Mukul Gagrani and Ashutosh Nayyar |
| CENG-2016-03 | CSim: A MOS switch-level simulatore by Fangzhou and Sandeep K. Gupta |
| CENG-2015-01 | Efficient Mechanism Design for Competitive Uplink Carrier Selection and Rate Allocation by Yanting Wu, Bhaskar Krishnamachari, George Rabanca, and Amotz Bar-Noy |
| CENG-2015-02 | The Optimism Principle: A Unified Framework for Optimal Robotic Network Deployment in An Unknown Obstructed Environment by Shangxing Wang, Bhaskar Krishnamachari and Nora Ayanian |
| CENG-2015-03 | Efficient Scheduling for Energy-Delay Tradeoff on a Time-Slotted Channel by Yanting Wu, Rajgopal Kannan, Bhaskar Krishnamachari |
| CENG-2015-04 | High Throughput Sketch Based Online Heavy Change Detection on FPGA by Da Tong and Viktor Prasanna |
| CENG-2015-05 | FPGA Based Accelerator for Pattern Matching in YARA Framework by Shreyas G Singapura, Yi-Hua E. Yangy, Anand Panangadan, Tamas Nemethz and Viktor K. Prasanna |
| CENG-2015-06 | Sketch Acceleration on FPGA and its Applications in Network Measurement by Da Tong and Viktor Prasanna |
| CENG-2015-07 | Fast Online Set Intersection for Network Processing on FPGA by Yun R. Qu and Viktor Prasanna |
| CENG-2015-08 | Optimizing Customer Selection for Sustainable Demand Response by Sanmukh Kuppannagari, Rajagopal Kannan, Charalampos Chelmis, Arash Tehrani and Viktor K. Prasanna |
| CENG-2014-01 | BackIP: Backpressure Routing in IPv6-Based Wireless Sensor Networks by Srikanth Nori, Suvil Deora, Bhaskar Krishnamachari |
| CENG-2014-02 | Efficient RAS support for 3D Die-Stacked DRAM by Hyeran Jeon, Gabriel H. Loh, Murali Annavaram |
| CENG-2014-03 | A Heuristic Logical Effort Approach for Gate Sizing for CNFET-Based Circuits by Da Cheng, Fangzhou Wang, Feng Gao, and Sandeep K. Gupta |
| CENG-2014-04 | Blade – A Timing Violation Resilient Asynchronous Design Template by Dylan Hand, Benmao Cheng1, Melvin Breuer, Peter A. Beerel |
| CENG-2014-05 | GPGPU Register File Management by Hardware Co-operated Register Reallocation by Hyeran Jeon and Murali Annavaram |
| CENG-2014-06 | Optimal Control for Epidemic Routing of Two Files with Different Priorities in Delay Tolerant Networks by Shangxing Wang, MHR. Khouzani, Bhaskar Krishnamachari and Fan Bai |
| CENG-2014-07 | Futility Scaling: High-Associativity Cache Partitioning (Extended Version) by Ruisheng Wang and Lizhong Chen |
| CENG-2014-08 | CTA-aware Prefetching for GPGPU by Hyeran Jeon, Gunjae Koo and Murali Annavaram |
| CENG-2014-09 | Accurate Model for Application Failure due to Transient Faults in Cache by Mehrtash Manoochehri and Michel Dubois |
| CENG-2013-1 | CPU Consolidation versus Dynamic Voltage and Frequency Scaling in a Virtualized Multi-Core Server: Which is More Effective and When by Inkwon Hwang and Massoud Pedram |
| CENG-2012-1 | AirSync - enabling Distributed MIMO with Full Spatial Multiplexing by Horia Vlad Balan, Ryan Rogalin, Antonios Michaloliakos, Konstantinos Psounis and Giuseppe Caire |
| CENG-2012-2 | Trojan detection via delay measurements: An approach to select paths and vectors to maximize effectiveness and minimize cost by Byeongju Cha and Sandeep K. Gupta |
| CENG-2012-3 | QoI-aware Analysis of Wireless Networks by Horia Vlad Balan, Ahmed Bahjat, Ramesh Govindan, Thomas LaPorta Kostas Psounis and Ram Ramanathan |
| CENG-2012-4 | Variability aware gate delay model considering MIS for ultra-low power/energy CMOS circuits by Prasanjeet Das and Sandeep K. Gupta |
| CENG-2012-5 | Scalable System-level Active Low-Power Mode with Bounded Latency by Daniel Wong and Murali Annavaram |
| CENG-2012-6 | Efficient post silicon validation via segmentation of the process variation envelope: Global vs. local variations by Prasanjeet Das and Sandeep K. Gupta |
| CENG-2012-7 | Efficient MAC for distributed multiuser MIMO systems by V. Balan, A. Michaloliakos, R. Rogalin, K. Psounis and G. Caire |
| CENG-2011-1 | Semi-Markovian User State Estimation and Policy Optimization for Energy Efficient Mobile Sensing by Yi Wang, Bhaskar Krishnamachari, Murali Annavaram |
| CENG-2011-2 | Reliability Aware Exceptions for Software Directed Fault Handling by Waleed Dweik, Murali Annavaram, Michel Duboi |
| CENG-2011-3 | Distributed Storage Codes Reduce Latency in Vehicular Networks by Maheswaran Sathiamoorthy, Alexandros G. Dimakis, Bhaskar Krishnamachari, Fan Bai |
| CENG-2011-4 | Wireless Body Area Networks: Where Does Energy Go? by Sangwon Lee and Murali Annavaram |
| CENG-2011-5 | A novel software-based defect-tolerance approach for application-specific embedded systems by Sandeep Gupta and Da Cheng |
| CENG-2011-6 | MCC: a High-Throughput Multi-Channel Data Collection Protocol for Wireless Sensor Networks by Ying Chen and Bhaskar Krishnamachari |
| CENG-2011-7 | Performance Bounds of Asynchronous Circuits: Lemmas and Theorems by Mehrdad Najibi and Peter A. Beerel |
| CENG-2010-1 | Shaping Packet Delay in Backpressure Stacks Using LIFO Service Priority by Scott Moeller, Bhskar Krishnamachari |
| CENG-2010-2 | Optimizing Content Dissemination in Heterogeneous Vehicular Networks by Joon Ahn, Bhaskar Krishnamachari, Fan Bai, Lin Zhang |
| CENG-2010-3 | Capturing variability in delay models beyond pin to pin by Prasanjeet Das and Sandeep K. Gupta |
| CENG-2010-4 | A systematic methodology to identify delay marginalities in a design during first silicon validation by Prasanjeet Das and Sandeep K. Gupta |
| CENG-2010-5 | Tag Spotting: communicating beyond carrier sense range by Horia Vlad Balan and Konstantinos Psounis |
| CENG-2010-6 | A Privacy Mechanism for Mobile-based Urban Traffic Monitoring by Chi Wang, Hua Liu, Bhaskar Krishnamachari and Murali Annavaram |
| CENG-2010-7 | On The Performance of Multiuser MIMO Mesh Networks by Mohammad Taha Bahadori & Konstantinos Psounis |
| CENG-2010-8 | Fast Data Collection in Tree-Based Wireless Sensor Networks by Ozlem Durmaz Incel, Amitabha Ghosh, Bhaskar Krishnamachari, Krishnakant Chintalapudi |
| CENG-2010-9 | Combinatorial Network Optimization with Unknown Variables: Multi-Armed Bandits with Linear Rewards by Yiai, Baskar Krishnamachari and Rahul Jain |
| CENG-2010-10 | Energy-Aware Hierarchical Cell Configuration: from Deployment to Operation by Kyuho Son, Eunsung Oh and Bhaskar Krishnamachari |
| CENG-2010-11 | Base Station Operation and User Association Mechanisms for Energy-Delay Tradeoffs in Green Cellular Networks by Kyuho Son, Hongseok Kim, Yung Yi, and Bhaskar Krishnamachari |
| CENG-2010-12 | On the Combinatorial Multi-Armed Bandit Problem with Markovian Rewards by Yi Gai, Bhaskar Krishnamachari! and Mingyan Liu |
| CENG-2009-1 | Dynamic MIPS Rate Stabilization in Out-of-Order Processors by Jinho Suh and Michel Dubois |
| CENG-2009-2 | Link Scheduling in a Single Broadcast Domain Underwater Networks by Pai-Han Huang, Ying Chen, Anil Kumar, and Bhaskar Krishnamachari |
| CENG-2009-3 | Sub-Carrier Allocation in OFDM Systems: Complexity, Approximability and Algorithms by Pai-Han Huang, Yi Gai, Bhaskar Krishnamachari |
| CENG-2009-4 | Compressed Sensing and Routing in Multi-Hop Networks by Sungwon Lee, Sundeep Pattem, Maheswaran Sathiamoorthy, Bhaskar Krishnamachari, Antonio Ortega |
| CENG-2009-5 | Handling Inelastic Traffic in Wireless Sensor Networks by Jiong Jin, Avinash Sridharan, Bhaskar Krishnamachari, and Marimuthu Palaniswami |
| CENG-2009-6 | Coordinated Sampling in Communication Constrained Sensor Networks using Markov Decision Processes by Shuping Liu, Anand Panangadan, Ashit Talukder, Cauligi S. Raghavendra |
| CENG-2009-7 | Scalable Node Level Computation Kernels for Parallel Exact Inference by Yinglong Xia, and Viktor K. Prasanna |
| CENG-2009-8 | A Simulation Study of IEEE 802.11 with Optimal Rate Control in Multi-hop Topologies by Apoorva Jindal and Konstantinos Psounis |
| CENG-2009-9 | Bargaining to Improve Channel Sharing between Selfish Cognitive Radios by Hua Liu, Allen MacKenzie, Bhaskar Krishnamachari |
| CENG-2009-10 | Backpressure Routing Made Practical by Scott Moeller, Avinash Sridharan, Bhaskar Krishnamachari, Omprakash Gnawali |
| CENG-2009-11 | Routing Without Routes: The Backpressure Collection Protocol by Scott Moeller, Avinash Sridharan, Bhskar Krishnamachari, Omprakash Gnawali |
| CENG-2009-12 | Approximate logic synthesis for error tolerant applications by Doochul Shin and Sandeep K. Gupta |
| CENG-2009-13 | Continuous Reliability Monitoring Using Adaptive Critical Path Testing by Bardia Zandian, Waleed Dweik, Suk Hun Kang, Thomas Punihaole, Murali Annavaram |
| CENG-2008-1 | Modeling Spatial and Temporal Dependencies of User Mobility in Wireless Mobile Networks by W. Hsu, T. Spyropoulosy, K. Psounis and A. Helmy |
| CENG-2008-2 | Hangout: A Privacy Preserving Location Based Social Networking Service by Murali Annavaram |
| CENG-2008-3 | Error-rate Estimation with Ones Counting by Melvin Breuer, Zhaoliang Pan |
| CENG-2008-4 | Achieving fast convergence for max-min fair rate allocation in Wireless Sensor Networks by Avinash Sridharan and Bhaskar Krishnamachari |
| CENG-2008-5 | Controlling Leakage Power with the Replacement Policy in Slumberous Caches by Nasir Mohyuddin, Rashed Bhatti, Michel Dubois |
| CENG-2008-6 | SlackSim: A Platform for Parallel Simulations of CMPs on CMPs by Jianwei Chen, Murali Annavaram, Michel Dubois |
| CENG-2008-7 | Investigating Backpressure based Rate Control Protocols for Wireless Sensor Networks by Avinash Sridharan, Scott Moeller and Bhaskar Krishnamachari |
| CENG-2008-8 | Algorithms for Fast Aggregated Convergecast in Sensor Networks by Amitabha Ghosh, Ozlem Durmaz Incel, V.S. Anil Kumar, and Bhaskar Krishnamachari |
| CENG-2008-9 | Multi-Channel Scheduling for Fast Convergecast in Wireless Sensor Networks by Ozlem Durmaz Incel, Amitabha Ghoshy, Bhaskar Krishnamachariy and Krishna Kant Chintalapudiz |
| CENG-2008-10 | TDMA scheduling feasibility of the Receiver Capacity Model by Avinash Sridharan and Bhaskar Krishnamachari |
| CENG-2008-11 | Characterization of GasP cells and analyzing the effects of the operating environments on timing verification by Prasad Joshi |
| CENG-2008-12 | Verifying RT constraints for GasP using PrimeTime by Prasad Joshi, Jonathan Gainsley |
| CENG-2008-13 | Static Replication Strategies for Content Availability in Vehicular Ad-hoc Networks by Shyam Kapadia, Bhaskar Krishnamachari, & Shahram Ghandeharizadeh |
| CENG-2008-14 | Negotiating Multichannel Sensing and Access In Cognitive Radio Wireless Networks by Hua Liux, Bhaskar Krishnamacharix, Qing Zhaoz |
| CENG-2008-15 | A Framework Design of Energy Efficient Mobile Sensing for Human State Recognition by Yi Wang, Jialiu Lin, Murali Annavaram, Quinn A. Jacobson, Jason Hong, Bhaskar Krishnamachari, Norman Sadeh |
| CENG-2007-1 | Modeling Search Costs in Wireless Sensor Networks by Krishnamachari & Ahn |
| CENG-2007-2 | Modelling BitTorrent-like Systems in Heterogeneous Environments by Psounis, Wei-Cherng Liao, Fragkiskos Papadopoulos |
| CENG-2007-3 | -Title and PDF Unavailable- by Dubois |
| CENG-2007-4 | Contention-Aware Analysis of Routing Schemes for Mobile Opportunistic Networks by Psounis and Apoorva |
| CENG-2007-5 | Test Generation Framework for Evaluation of Wireless MAC Protocols by Shamim Begum |
| CENG-2007-6 | An Efficient PIM Architecture for Computer Graphics by Gupta and Cha |
| CENG-2007-7 | Efficient Identification of Uncongested Links for Topological Downscaling of Internet-like Networks by Psounis and Papadopoulos |
| CENG-2007-8 | An Analytical Study of Fundamental Mobility Properties for Encounter-based Protocols by Psounis, Spyropoulos, Jindal |
| CENG-2007-9 | Contention-Aware Performance Analysis of Mobility-Assisted Routing by Psounis and Jindal |
| CENG-2007-10 | On the Performance Evaluation of Encounter-based Worm Interactions Based on Node Characteristics by Helmy and Tanachaiwiwat |
| CENG-2007-12 | The Achievable Rate Region of 802.11-Scheduled Multi-hop Networks by Apoorva Jindal and Konstantinos Psounis |
| CENG-2007-13 | Performance of a Propagation Delay Tolerant ALOHA Protocol for Underwater Wireless Networks by Joon Ahn and Bhaskar Krishnamachari |
| CENG-2006-1 | An Evaluation of Availability Latency in Carrier-Based Vehicular Ad-hoc Networks by Krishnamachari, Ghandeharizadeh & Kapadia |
| CENG-2006-3 | Derivations of the Expected Energy Costs of Search and Replication in Wireless Sensor Networks by Krishnamachari & Ahn |
| CENG-2006-3 | Derivations of the Expected Energy Costs of Search and Replication in Wireless Sensor Networks by Krishnamachari & Ahn |
| CENG-2006-4 | Sequence Based Localization in Wireless Sensor Networks by Krishnamachari & Yedavalli |
| CENG-2006-5 | -Title and PDF Unavailable- by Gupta & Shahidi |
| CENG-2006-6 | The Power of Choice in Random Walks: An Empirical Study by Krishnamachari & Avin |
| CENG-2006-7 | Pricing Reliable Routing in Wireless Networks of Selfish Users by Krishnamachari & Liu |
| CENG-2006-8 | Using Heterogeneity to Enhance Random Walk-based Queries by Krishnamachari, Zuniga & Avin |
| CENG-2006-9 | Impact of Capture on Multihop Wireless Networks in an Optimal Rate Control Framework by Krishnamachari, Syed & Jun |
| CENG-2006-10 | Analysis of Slotted Multi-Access Techniques for Wireless Sensor Networks by Krishnamachari & Yedavalli |
| CENG-2006-11 | LAMA: Location-Aware Medium Access for Wireless Sensor Networks by Krishnamachari & Yedavalli |
| CENG-2006-12 | Fundamental Mobility Properties for Realistic Performance Analysis of Intermittently Connected Mobile Networks by Psounis & Apoorva |
| CENG-2006-13 | MobIGames: Mobile Interaction Games with Wireless Devices by Krishnamachari, Kapadia & Wang |
| CENG-2006-14 | Enhancement of the IEEE 802.15.4 MAC Protocol for Scalable Data Collection in Dense Sensor Networks by Krishnamachari &Yedavali |
| CENG-2006-15 | On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus by Pinkston & Ainsworth |
| CENG-2005-1 | Modeling Spatially Correlated Data in Sensor Networks by Psounis and Jindal |
| CENG-2005-2 | Canonical Representation and Efficient Synthesis of Quantum Logic Circuits by Pedram and Abdollahi |
| CENG-2005-3 | Efficient Asynchronous Bundled-Data Pipelines for DCT Matrix-Vector Multiplication by Beerel and Tugsinavisut |
| CENG-2005-5 | Structural Delay Testing Under Restricted Scan of Latch-based Pipelines with Time Borrowing by Gupta, Chung |
| CENG-2005-6 | Energy Efficient Joint Scheduling and Power Control for Wireless Sensor Networks by Krishnamachari, Lu |
| CENG-2005-7 | Performance Preserving Topological Downscale of Internet-like Networks by F. Papadopoulos, K. Psounis, R. Govindan |
| CENG-2005-8 | High-Speed QDI Asynchronous Pipelines TVLSI-00128-2003 by Beerel and Recep Ozdag |
| CENG-2005-9 | ConfigurationCompression for FPGA-based Embedded Systems by Prasanna and Dandalis |
| CENG-2005-11 | Adaptive Allocation of Independent Tasks to Maximize Throughput by Prasanna and Bo Hong |
| CENG-2005-12 | Using Wireless Advantage for Congestion Control in Wireless Sensor Networks by Coe |
| CENG-2005-13 | Using Wireless Advantage for Congestion Control in Wireless Sensor Networks by Kiran Yedavalli |
| CENG-2005-14 | Optimizing Data Replication for Expanding Ring-based Queries in Wireless Sensor Networks by Krishnamachari and Ahn |
| CENG-2005-15 | An Efficient Algorithm for Resource Sharing in Peer-to-Peer Networks by Psounis, Papadopoulos and Liao |
| CENG-2005-16 | Comparative Analysis of Push-Pull Query Strategies for Wireless Sensor Networks by Krishnamachari, & Kapadia |
| CENG-2004-01 | SIFT: A Low-complexity Scheduler for Reducing Flow Delays in the Internet K.Psounis, A. Ghosh, B. Prabhakar |
| CENG-2004-03 | SHRiNKing Web Server Farms: A Method for Scaleable Performance Prediction and Measurement K. Psounis |
| CENG-2004-04 | Algorithm Design and Synthesis for Wireless Sensor Networks by Prasanna and Bakshi |
| CENG-2004-06 | Dynamic Timing Analysis by Gupta, Huang |
| CENG-2004-07 | Constrained Flow Optimization with Applications to Data Gathering in Sensor Networks by Prasanna and Hong |
| CENG-2004-09 | Constructing Topographic Maps in Networked Sensor Systems by Prasanna, Bakshi, Singh |
| CENG-2004-10 | Modeling of Spatially-Correlated Sensor Network Data by Psounis and Jindal |
| CENG-2004-11 | Efficient Routing in Intermittently Connected Mobile Networks: The Single-Copy Case by Raghavendra, Psounis, Akis |
| CENG-2004-12 | Efficient Routing in Intermittently Connected Mobile Networks: The Multiple-Copy Case by Raghavendra, Psounis, Akis |
| CENG-2004-13 | Performance Preserving Topological Downscaling of Internet-Like Networks by Papadopoulos, Psounis, Govindan |
| CENG-2004-14 | The Impact of Blacklisting on Data Gathering Trees in Wireless Sensor Networks by Krishnamachari, Urgaonkar |
| CENG-2004-15 | Energy-Efficient Data Gathering with Tunable Compression in Wireless Sensor Networks by Yu Yang |
| CENG-2004-16 | Ecolocation: A Technique for RF Based Localization in Wireless Sensor Networks by Krishnamachari, Yedavali, Ravula, Srinivasan |
| CENG-2004-17 | Trends Toward On-Chip Networked Microsystems by Pinkston and Shin |
| CENG-2003-01 | Designing Multiple Scan Chains For System On Chips (SOC) by Md. Saffat Quasem, Sandeep Gupta |
| CENG-2003-02 | Distributed Adaptive Task Allocation in Heterogeneous Computing Environments to Maximize Throughput by Bo Hong, Viktor Prasanna |
| CENG-2003-03 | Optimizing Graph Algorithms for Improved Cache Performance by Joon-Sang Park, Michael Penner, Viktor Prasanna |
| CENG-2003-04 | Supporting Topographic Queries in Sensor Networks by Amol Bakshi, Mitali Singh, Viktor K. Prassana |
| CENG-2003-05 | Exploring Energy-Latency Tradeoffs for Data Gathering in Wireless Sensor Networks by Yang Yu, Bhaskar Krishnamachari, Viktor K. Prasanna |
| CENG 02-01 | Optimizing Graph Algorithms for Improved Cache Performance by Joon-Sang Park, Michael Penner, and Viktor K. Prasanna |
| CENG 02-02 | An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes by Zhigang Jinag and Sandeep Gupta |
| CENG 02-03 | A method for Applying Double Scheme Dynamic Reconfiguration over InfiniBand™ by Tomithy Pinkston, Bilal Zafar, and Jose Duato |
| CENG 02-07 | Integrating Complete-System and User-level Performance/Power Simulators: This Sim Wattch Approach by Jianwei Chen, Michel Dubois and Per Stenström |
| CENG 02-15 | Memory Hierarchy Performance of Tiling and Block Data Layout by Neungsoo Park, Bo Homg and Viktor Prasanna |
| CENG 02-16 | Gate Delay Modeling for Multiple To-non-controlling Stimuli by Liang Chi Chen, anf Melvin Breuer |
| CENG 01-01 | Techniques for Efficient Network Utilization in Multiprocessor/Multicomputer Systems by Yong Ho Song and Timothy Mark Pinkston |
| CENG 01-03 | Asynchronous 1 of n Logic Using Single-Track Protocol by Peter A. Beerel and Marcos Ferretti |
| CENG 01-04 | Synthesis and Optimization of Application-Specific Intranets by Synthesis and Optimization of Application-Specific Intranets |
| CENG 00-01 | A New Framework for Static Timing Analysis, Incremental Timing Refinement & Timing Simulation by Liang-Chi Chen, Sandeep Gupta and Melvin Breuer |
| CENG 00-02 | I-Structure Software Caches: Exploiting Global Data Locality in Non-Blocking Multithreaded Architectures by Wen-Yen Lin |
| CENG 00-03 | The Case for Virtually-Addressed Memory Hierarchies by Xiaogang Qiu and Michel Dubois |
| CENG 00-04 | Toward Virtually Addressed Memory Hierarchies by Xiaogang Qiu |
| CENG 00-05 | EE577b VLSI Design Project: A Design of a Turbo Decoder Chip by Pornchai Pawawongsak |
| CENG 00-06 | An Exact Fault Simulation for Systems on Silicon that Protects Each Cores Intellectual Property (IP) by |
| CENG 00-07 | Test Generation For Crosstalk Noise in VLSI Circuits by Wei-Yu Chen |
| CENG 99-01 | Test Generation for Path-Delay Faults in Iterative Logic Arrays by Nabil Abdulrazzaq and Sandeep Gupta |
| CENG 99-02 | Dynamic Power Management Based: A Continuous-Time Stochastic Approach by Qinru Qui, Qing Wu, and Masssoud Pedram |
| CENG 99-03 | MCOMA: A Multithreaded COMA Architecture by Halima M. El Naga |
| CENG 99-04 | LT-RTPG: A New Test Per Scan BIST TPG for Low Heat Dissipation by S. Wang and Sandeep K. Gupta |
| CENG 99-06 | Optimizing Average-Case Performance in the Technology Mapping of Asynchronous Circuits by Wei-Chun Chou |
| CENG 99-07 | Benchmarking of HPC System by Dongsoo Kang, Henry W. Park, Jinwoo Suh, Viktor K. Prasanna and Sharad N. Gavali |
| CENG 99-08 | An Efficient Algorith for Large Scale Metrics Transposition by Jinwoo Suh, Santosh Narayanan, and Viktor k. Prasanna |
| CENG 99-09 | Design & Perormance of SMMPs with Asynchronous Caches by Fong Pong, Michel Dubois, and Ken Lee |
| CENG 99-10 | Performance Analysis of Asynchronous Circuits and Systems by Aiguo Xie |
| CENG 98-01 | A Methodology for transforming Memory Tests for In-system Testing of Direct Mapped Cache Tags by Sultan Al-Harbi and Sandeep Gupta |
| CENG 98-02 | Design and Performance of the Software-Controlled Coma by Adian Moga |
| CENG 98-03 | Generalized Input Reduction BIST TPG for Cluster Interconnection Test at Board Levels by C-H Chiang and Saneep Gupta |
| CENG 98-04 | Codex-dp: Co-design of Communicating Systems Using Dynamic Programming by Jui-Ming Chang and Massoud Pedram |
| CENG 98-05 | Design of Application Software for Embedded Signal Processing by Wenheng Liu and Viktor K. Prasanna |
| CENG 98-06 | T-Robust Testing for Delay Faults by Suriya Natalrajan, Sandeep Gupta and Melvin Breuer |
| CENG 99-07 | A New Path-Oriented Effect-Cause Methodology to Diagnose Delay Failures by Yuan-Chieh Hsu and Sandeep K. Gupta |
| CENG 98-08 | Options for Dynamic Address translation in COMAs by Xiaogang Qui and Michel Dubois |
| CENG 98-09 | Parallel Implementation of a Class of Adaptive Signal Processing Applications by Myungho Lee and Viktor K. Prasanna |
| CENG 98-10 | Synthesis of Area-Efficient and High-Throughput Rate Data Format Converters by Jongwoo Bae and Viktor K. Prasanna |
| CENG 98-11 | Cycle-Accurate Macro Models for RT-Level Power Analysis by Qing Wu and Massoud Pedram |
| CENG 98-16 | Automatic Array Partitioning and Distributed Array Compilation for Efficient Communication by Hung-Yu Tseng |
| CENG 98-17 | Analysis of Variance in Micropipelines by Aiguo Xie and Peter Beerel |
| CENG 98-19 | Micro Processor Power Estimation Using Profile Drive Program Synthesis by Cheng-Ta Hsieh and Massoud Pedram |
| CENG 98-20 | Anaysis and Implementation of Optoelectronic Network Routers by Mongkol Raksapatcharawong |
| CENG 98-21 | Logical Physical Co-Design for Deep Submicron Digital Circuits by Amir H. Salek. Jinan Lou and Massoud Pedram |
| CENG 98-22 | Efficient Algorithms for Block-Cyclic Array Redistribution between Processor Sets by Neugsoo Park and Viktor K. Prasanna |
| CENG 98-23 | A Dynamic Resource Allocation and Measurement-Based Call Admission Control Algorithm for Integrated Service Networks by Tien Chien Yu and John Silvester |
| CENG 98-24 | Interaction between Multimedia and Traditional (FTP/WEB) Applications: An Experimental Performance Study by Gurvinder Singh and John Silvester |
| CENG 98-25 | Assisted Execution by Michel Dubois and Yong Ho Song |
| CENG 98-26 | Studies on the Impact of Long-term Correlation on Computer Network Performance: Part I Link-Layer Modeling by Hany D. Alsaialy and John Silvester |
| CENG 98-27 | Studies on the Impact of Long-term Correlation on Computer Network Performance: Part II Link-Layer Modeling by Hany D. Alsaialy and John Silvester |
| CENG 98-28 | Accuracy Sensititive Word-Length Selection for Algorithm Optimization by Suhrid Ashok Wadekar |
| CENG 98-29 | Probabilistic Analysis of Power Dissipation in VLSI Systems by Radu Marculescu |
| CENG 98-30 | Studies on the Impact of Long-Term Correlation on Computer Network Performance by Hany D. Alsaialy |
| CENG 98-31 | Optimization of BIST Resources During High-Level Systems by Ishwar Parulkar |
| CENG 97-01 | Implementation of Deadlock Detection in a Simulated Interconnection Network Environment by Sugath Warnakulasuriya and Timothy Pinkston |
| CENG 97-02 | Memory Organizations in Hybrid DSM: A Performance Comparison by Adrian Moga, Alain Gefflaut, and Michel Dubois |
| CENG 97-03 | Hardware vs. Software Implementation of COMA by Adrian Moga, Alain Gefflaut, and Michel Dubois |
| CENG 97-04 | Hybrid Compiler/Hardware Prefetching for Multiprocessors Using Low-Overhead Cache Miss Traps by Jonas Skeppstedt and Michel Dubois |
| CENG 97-06 | Variations in Electrical Values and Their Ramifications on Correct Circuit Operation by S. Natarajan, M.A. Breuer and S. K. Gupta |
| CENG 97-07 | Vector Compaction Using Hierarchical Markov Models by R. Marculescu, D. Marculescu and M. Pedram |
| CENG 97-08 | FSM Analysis Using High-Order Markov Models by R. Marculescu, D. Marculescu and M. Pedram |
| CENG 97-09 | Statistical Estimation of Distribution of Power Dissipation in VLSI Circuits by Chih-Shun Ding and M. Pedram |
| CENG 97-10 | Efficient Algorithms for Block-Cyclic Redistribution of Arrays by Young Won Lim, Prashanth B. Bhat and Viktor K. Prasanna |
| CENG 97-11 | The Effectiveness of SRAM Network Caches in Clustered DSMs by Young Won Lim, Prashanth B. Bhat and Viktor K. Prasanna |
| CENG 97-12 | Analytic Models for Crosstalk Delay and Pulse Analysis for Non-Ideal Inputs by Weiyu Chen, Melvin Breuer and Sandeep Gupta |
| CENG 97-13 | Early System Architecture Optimization for Multi-Chip Systems by Dong-Hyun Heo |
| CENG 97-14 | Improving the Quality of Safe BDD Minimization Using Don't Cares by Youngpyo Hong and Peter Beerel |
| CENG 97-15 | Minimizing BIST Resource Requirements of Data Paths Using Redundancy by Iswar Parulkar, Sandeep Gupta, and Melvin Breuer |
| CENG 97-16 | An Adaptive Multi-Class Call Admission Control for Multimedia Wireless Networks by Ebrahim Abdulrahman Ismail |
| CENG 97-17 | BIST TPG for Faults in Backplane Interconnect by Chen-Huan Chiang and Sandeep Gupta |
| CENG 97-18 | Portable Implementation of Real-Time Signal Processing Benchmarks on HPC Platforms by Jinwoo Suh and Viktor K. Prasanna |
| CENG 97-19 | Steady-State Probability Estimation in FSMs Considering High-Order Temporal Effects by D. Marculescu, R. Marculescu, and M. Pedram |
| CENG 97-20 | Efficient State Classification of Finite Markov Chains by Aiguo Xie and Peter A. Beerel |
| CENG 97-21 | Accelerating Markovian Analysis of Asynchronous Systems Using String-based State Compression by Aiguo Xie and Peter A. Beerel |
| CENG 97-22 | Fanout Optimization under a Submicron Transistor-Level Delay Model by Pasquale Cocchini and Massoud Pedram |
| CENG 97-23 | EZDB: A Framework for Easy Evaluations of Commercial Applications by Kangwoo Lee, Jigar Thakkar, and Michel Dubois |
| CENG 97-24 | Empirical Performance Modeling of Multiprocessors Based on Data-Sharing Analysis by Kangwoo Lee |
| CENG 97-25 | Efficient Reachability Analysis of Large Finite State Machines Using Don't Care-Based BDD Minimization by Youpyo Hong and Peter A. Beerel |
| CENG 97-26 | The Physical Design of RPM by Jaeheon Jeong, Yongho Song, and Michel Dubois |
| CENG 97-27 | Implementation of a CC-NUMA on RPM by Jaeheon Jeong, Yongho Song, Adrian Moga and Michel Dubois |
| CENG 97-28 | Rapid Hardware Prototyping on RPM-2: Methodology and Experience by Michel Dubois, Alain Gefflaut, Jaeheong Jeong, Adrian Moga, and Koray Oner |
| CENG 97-29 | Theory and Practice in Siptem-Level Design of Application-Specific Heterogeneous Multi-processors by Yosef Howriel Tirat-Hefen |
| CENG 96-01 | Modeling Survey: The Relationship between Environments, Services, and Network Performance in Wireless by Te-Kai Liu and John A. Silvester |
| CENG 96-02 | Retransmission Control and Fairness Issue in Mobile Slotted ALOHA Networks with Fading and Near-far Effect by Te-Kai Liu and John A. Silvester, and Andreas Polydoros |
| CENG 96-03 | Design and Evaluation of a Software-Controlled COMA by Alain Gefflaut, Adrian Moga, Jaeheon Jeong, and Michel Dubois |
| CENG 96-04 | Computing ODCs and function Minimization Targeting Low Power by Sasan Iman and Massoud Pedram |
| CENG 96-05 | Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming by Jaewon Oh, Iksoo Pyo and Massoud Pedram |
| CENG 96-06 | Estimating BIST Resources in High-level Synthesis by Ishwar Parulkar, Sandeep K. Gupta and Melvin A. Breuer |
| CENG 96-07 | A Satisfiability-Based Test Generator for path Delay Faults in Combinational Circuits by Chih-Ang Chen and Sandeep Gupta |
| CENG 96-08 | A Framework for Coarse Grain Parallel Execution of Functional Program by Dae-Kyun Yoon |
| CENG 96-09 | Bounds on Pseudo-Exhaustive Test Lengths by Rajagopalan Srinivasan, Sandeep K. Gupta, and Melvin A. Breuer |
| CENG 96-10 | Stateful Computations in Functional Languages by Yung-Syau Chen |
| CENG 96-11 | Statistical Sampling for VLSI Circuits by Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu and Massoud Pedram |
| CENG 96-12 | Multi-level Logic Synthesis Based on Function Decomposition by Kuo-Rueih Ricky Pan |
| CENG 96-13 | How to Minimize Energy Using Multiple Supply Voltages by JuiMing Chang and Massoud Pedram |
| CENG 96-14 | Vector Compaction Using Dynamic Markov Models by Radu & Diana Marculescu and Massoud Pedram |
| CENG 96-15 | Performance Modeling and Design Trade-offs of Wireless Communication Networks with Heterogeneous by Te-Kai Liu |
| CENG 96-16 | Constrained Sequence Generation Using Schochastic Sequential Machines by D. Marculescu, R. Marculescu and M. Pedram |
| CENG 96-17 | A Trace-Driven Simulation of an ATM Queueing System by Gilberto Mayor and John Silvester |
| CENG 96-18 | An ATM Queueing System with Long-Range Dependent Traffic: Providing QoS Guarantees by Gilberto Mayor and John Silvester |
| CENG 96-19 | High Performance Parallel Logic programming on Distributed Shared Memory Multiprocessors by Hiecheol Kim |
| CENG 96-20 | Test Generation 7 Embedding for Built-in Self-Test by C. A. Chen |
| CENG 96-22 | ATPG for Heat Dissipation Minimization for Scan Testing by Seongmoon Wang and Sandeep K. Gupta |
| CENG 96-23 | System-Level Estimation of Energy and Power by Surid Wadekar and Alice Parker |
| CENG 96-24 | Statistical Design of Macro-models for RT-Level Power by Qing Wu and Massoud Pedram |
| CENG 96-25 | Rapid synthesis of Multi-chip Systems by Dong Hyun Heo, C. P. Ravikumar, and Alice Parker |
| CENG 96-26 | Versatile Multichip Digital System Architecture Synthesis Tools by Dong Hyun Heo, C. P. Ravikumar, and Alice Parker |
| CENG 96-27 | Generalized Input Reduction BIST for Interconnection faults via Boundary Scan at the board Level by Chen-Huan Chiang and Sandeep Gupta |
| CENG 96-28 | High Quality Robust Tests for Path Delay Faults by Liang-Chi Chen, Sandeep Gupta, Melvin A. Breuer |
| CENG 96-29 | Optimal Synthesis of Application Specific Heterogeneous Multiprocessors by Y.G. Tirat-Geen and Alice Parker |
| CENG 96-30 | Optimal ILP-based Approach for Throughput Optimization Using Algorithm/Architecture Matching and retiming by Y.G. Tirat-Geen and Alice Parker |
| CENG 96-31 | MESGA: An Approach to System-Level Design of Application-Specific Heterogeneous by Y.G. Tirat-Geen and Alice Parker |
| CENG 96-32 | Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors by Y.G. Tirat-Geen and Alice Parker |
| CENG 96-33 | System-Level Design of Application-Specific Heterogeneous Multiprocessors in the presence of Uncertainty by Y.G. Tirat-Geen and Alice Parker |
| CENG 96-34 | Turn Selection Enhancements to Deadlock Recovery Algorithms by Timothy M. Pinkston, Joseph Borsody and William Kostes |
| CENG 96-35 | Parallelism Control in Multithreaded Multiprocessors by Namhoon Yoo |
| CENG 96-36 | Automatic Code Partitioning for Distributed Memory Multiprocessors (DMMs) by Moez Ayed |
| CENG 96-37 | An Efficient Heuristic for Code Partitioning by Moez Ayed and Jean-Luc Gaudiot |
| CENG 95-01 | Nomadic Threads: A Runtime Approach for Managing Remote Memory Accesses in Multiprocessors by Stephen Jenks and Jean-Luc Gaudiot |
| CENG 95-02 | Data Path Allocation Techniquest for High-Level Synthesis of Low BIST Area Overhead Designs by Ishwar Parulkar, Sandeep Gupta and Melvin Breuer |
| CENG 95-03 | Power Efficient Register Assignment by Jui-Ming Chang and Massoud Pedram |
| CENG 95-04 | Switching Activity Estimation Based on Conditional Independence by Radu Marculescu, Diana Marculescu and Massoud Pedram |
| CENG 95-05 | Effects of Asynchronism on the Convergence Rate of A Class of iTERATIONS by Aydin Uresin and Michel Dubois |
| CENG 95-06 | Performance of Asynchronous Linear Iterations With Random Delays by Adrian C. Moga and Michel Dubois |
| CENG 95-07 | Implementation And Performance Of Asynchronous And Synchronous Data Classification Algorithms by Adrian C. Moga and Michel Dubois |
| CENG 95-08 | ASPEED Cache Coherence Protocol For An Optical Multi-Access Interconnect Architecture by Joon-Ho Ha and Timothy M. Pinkston |
| CENG 95-10 | Parallel HO-PD Benchmark on the IBM SP2 by M. Arakawa, Z. Xu and K. Hwang |
| CENG 95-11 | Parallel APT Benchmark on the IBM SP2 by M. Arakawa, Z. Xu and K. Hwang |
| CENG 95-12 | Parallel General Benchmark on the IBM SP2 by M. Arakawa, Z. Xu and K. Hwang |
| CENG 95-13 | Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing by Kai Hwang and Zhiewei Xu |
| CENG 95-14 | Modeling Communication Overheard: MPI and MPL Performance on the IB SP2 Multicomputer by Kai Hwang and Zhiewei Xu |
| CENG 95-15 | Early Pediction of MPP Performance of Workload and Overhead Quantification A Case Study of the IBM SP2 System by Kai Hwang and Zhiewei Xu |
| CENG 95-16 | Power Efficient Module Allocation and Binding by Jui-Ming Chang and Massoud Pedram |
| CENG 95-17 | Normalized NETLENGTHS: A Measure of Routing Cost for Logic Synthesis by H. Vaishnav and Massoud Pedram |
| CENG 95-18 | Delay Optimal Partitioning Targeting Low Power VLSI Circuits by Hirendu Vaishnav and Massoud Pedram |
| CENG 95-19 | Simulation of the Communication Libraries of the CM-5 on UNIX Workstations by Nicolas Guerin and J-L Gaudiot |
| CENG 95-20 | Optimizatin of Post-Layout Area, Delay and Power Dissipation by Hirendu Vaishnav |
| CENG 95-21 | Deadlock-Free Adaptive Wormhole Routing with Disha Concurrent by Anjan K. V., Timothy M. Pinkston, Jose Duato |
| CENG 95-22 | Modeling Free-Space Optical k-ary n-cube Wormhole Networks by Mongkol Raksapatcharawong and Timothy M. Pinkston |
| CENG 95-23 | Multiprocessor Emulation with RPM: Early Experience by Michel Dubois, Allain Gefflaut, Jaeheon Jeong, Adrian Moga, and Koray One |
| CENG 95-24 | Maximum Throughput and the Maximum Balanced Throughput of Mobile Slotted ALOHA Networks by Te-Kai Liu and John A. Silvester |
| CENG 95-25 | RT-Level Power Analysis Using Information Theoretic Measures by Diana Marculescu, Radu Marculescu, and Massoud Pedram |
| CENG 95-26 | SPEED DMON: Cache Coherence on an Optical Multi-channel Interconnect Architecture by Joon-Ho Ha and Timothy M. Pinkston |
| CENG 95-27 | PLA Minimization for Low Power VLSI Designs by S. Iman. C.Y Tsui and M. Pedram |
| CENG 95-28 | Computing Network DCs and Function Minimization Targeting Low Power by Sasan Iman and Massoud Pedram |
| CENG 94-01 | Formal Verification of Complex Coherence Protocols Using Symbolic State Models by Fong Pong and Michel Dubois |
| CENG 94-02 | Test Embedding With Discrete Logarithms by Mody Lempel, Sandeep K. Gupta and Melvin A. Breuer |
| CENG 94-03 | Unifed System Construction (USC) Tools by Alice Parker |
| CENG 94-04 | Clock Grouping: A Low Cost DFT Methodology for Delay Testing by Wen-Chang Fang and Sandeep K. Gupta |
| CENG 94-05 | Logic Leve Power Estimation Considering Spatiotemporal Correlations by Logic Leve Power Estimation Considering Spatiotemporal Correlations |
| CENG 94-06 | Multi-Level Network Optimization Targeting Low Power by S. Iman and M. Pedram |
| CENG 94-07 | Low Power State Assignment Targeting Two-and Multi-Level Logic Implementations by C-Y Tsui, C-A Chen, M. Pedram. And A.M. Despain |
| CENG 94-08 | Random Pattern Testable Logic Synthesis by Chen-Huan Chiang and Sandeep K. Gupta |
| CENG 94-09 | A Binding Environment for Processing Logic prorams on Large-Scale Parallel Architectures by Hiecheol Kim and Jean-Luc Gaudiot |
| CENG 94-10 | Parallel APT Benchmark on the IBM SP2 by M. Arakawa, Z. Xu and K. Hwang |
| CENG 95-12 | The NDF Model: Processing Logic Programs on Large-Scale Parallel Architectures by Hiecheol Kim and Jean-Luc Gaudiot |
| CENG 95-13 | Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing by Kai Hwang and Zhiewei Xu |
| CENG 94-11 | A Design System To Support Built-In Self-Test of VLSI Circuits Using Bilbo-Oriented test Methodologies by Sen-Pin Lin |
| CENG 94-12 | Zero-Aliasing for Modeled Faults by Mody Lempel and Sandeep K. Gupta |
| CENG 94-13 | Recombination, Selection, and the Genetic Construction of Computer Programs by Walter Alden Tackett |
| CENG 94-14 | Jitter at an ATM Multiplexer in The Presence of Correlated Traffic by Ram Krishnan, John A. Silvester and C. S. Raghavendra |
| CENG 94-15 | The U.S.C Multiprocessor TestBed Project: Project Overview by Michel Dubois, L. Barroso, S. Iman, J. Jeong, k. Oner and K. Ramamurthy |
| CENG 94-16 | Functional Prograaming and Fine-Grain Multithreading for High-Performance Parallel Computing by Chihyun Kim |
| CENG 94-17 | System-Level Design Techniques and Tools for Synthesis of Application-Specific Digital Systems by Chih-Tung Chen |
| CENG 94-18 | A Methodology and Design Tools to Support System-Leel VLSI Design by Kayhan Kucukcakar and Alice C. Parker |
| CENG 94-19 | Approximate Performance models of Multimedia Communications Over Fast Packet-Switched Networks by Stanley Shiouming Wang |
| CENG 94-20 | High-Level Synthesis of Memory-Intensive Application-Specific Systems by Pravil Gupta |
| CENG 94-21 | An Integrated Test Controller Synthesis System by Debaditya Mukherjee |
| CENG 94-22 | A Comparative Study of The Programmability of a Signal Processing Application in an MIMD and an SIMD Multiprocessor by Dae-Kyun Yoon and Jean-Luc Gaudiot |
| CENG 94-23 | DISHA: An Efficient, Fully Adaptive Deadlock Recovery Scheme by Anjan K.V. and Timothy Mark Pinkston |
| CENG 94-24 | D-BMAP Models for Performance Evaluation of ATM Networks by John A. Silvester, Nelson L.S. Fonseca and Stanely S. Wang |
| CENG 94-25 | Queueing Network Models for Multiple Class Broadband Integrated Services Digital Networks by Nelson Luis Saldanha da Fonseca |
| CENG 94-26 | Pseudo-Exhaustive Built-In Self-Test System for Logic Circuits by Rajagopalan Srinivasan |
| CENG 94-27 | Factored Edge-Valued Binary Decision Diagrams and Their Application to Matrix Representation and Manipulation by Paul Tafertshofer and Massoud Pedram |
| CENG 94-28 | A Specification of The Array Semantics for Sisal 2.0 by Yung-Syau Chen and Jean-Luc Gaudiot |
| CENG 94-29 | An Analytical Model for Multi-group Slotted ALOHA With Capture by Te-Kai Liu, John A. Silvester and Andreas Polydoros |
| CENG 94-30 | Performance Evaluation of R-ALOHA in Distributed Packet Radio Networks with Hard Real-Time Communications by Te-Kai Liu, John A. Silvester and Andreas Polydoros |
| CENG 94-31 | A General Performance Model for Mobile Slotted ALOHA Networks with Capture by Te-Kai Liu, John A. Silvester and Andreas Polydoros |
| CENG 94-33 | Scan Chaining and Test Scheduling in an Integrated Scan Design System by Sridhar Narayanan |
| CENG 94-34 | A Practical BIST TPG Design Methodology by Chih-Ang Chen and Sandeep K. Gupta |
| CENG 94-35 | Constructing Minimal Spanning Trees with Bounded Path Length by Iksoo pyo, Jaewon Oh and Massoud Pedram |
| CENG 94-36 | An Exact Framework for Post-Layout Timing Correction by Hirendu Vaishnav and Massoud Pedram |
| CENG 94-37 | Built-in Self-Test for Modeled Faults by Mody Lempel |
| CENG 94-38 | Data-Flow Assembly Lanugage by Moez Ayed and Jean-Luc Gaudiot |
| CENG 93-01 | A Direct Array Handling Technique for Non-strict and Parallel Accesses in a Multithreaded Architecture by Chinhyun Kim and Jean-Luc Gaudiot |
| CENG 93-02 | The Detection and Elimination of Useless Misses in Multiprocessors by Michel Dubois, Jonas Skeppstedt, Luvio Ricciulli, Krishnan Ramamurthy, and Per Stenstrom |
| CENG 93-03 | Estimating the Loss Probability in a Multiplexer Loaded with Multipriority MMPP Streams by Nelson L.S. Fonseca and John A. Silvester |
| CENG 93-04 | Scalable Data Parallel Implementatons of object Recognition using Geometric Hashing by A. Khokhar, H. Kim, V. Prasanna, and C. Wang |
| CENG 93-05 | A Discrete-Time Performance Model for Integrated Services ATM Multiplexers by Shiouming Stanley Wang and John A. Silvester |
| CENG 93-06 | Synthesis of Application-specific Multiprocessor Systems by Shiouming Stanley Wang and John A. Silvester |
| CENG 93-07 | HISS: A Prototype Program for Hierarchical Storage Synthesis by Pravil Gupta and Alice Parker |
| CENG 93-08 | An Efficient Partitioning Strategy for Pseudo-exhaustive Testing by R. Srinivasan, S. Gupta, and M. Breuer |
| CENG 93-11 | FGILP: An Integer Linear Program Solver Based on Function Graphs by Yung-Te Lai, Massoud Pedram and Sarma B.K. Vrudhula |
| CENG 93-12 | Efficient Estimation of Dynamic Power Dissipation by Chi-Ying Tsui, Massoud Pedram and Alvin M. Despain |
| CENG 93-13 | Architecture and Routability Analysis for Row-Based FPGAs by Massoud Pedram, B. Nobandegani, and Bryan T. Press |
| CENG 93-14 | Efficient Symbolic Simulation under the Extended Bounded Delay Model for Transition Mode Timing Analysis by Chihshun Ding and Massoud Pedram |
| CENG 93-15 | Wire Delay Estimation by Pravil Gupta and Alice Parker |
| CENG 93-16 | PLA Delay Estmation by Pravil Gupta and Alice Parker |
| CENG 93-17 | Performance Analysis of Four Memory Consistency Models for Multithreaded Multiprocessors by Yong-Kim Chong and Kai Hwang |
| CENG 93-18 | Hardwired Barriers for Fast Synchronization of Concurrent Processes on Scalable Multiprocessors by Shisheng Shang and Kai Hwang |
| CENG 93-19 | Multicoloring of Grid-Structured PDE Solvers for Parallel Execution on Multiprocessors by H.C. Wang and Kai Hwang |
| CENG 93-20 | Data Prefetching Effects on the Performance of Multithreaded Multiprocessors by Weighua Mao, Kai Hwang, and Rafeal H. Saavedra |
| CENG 93-21 | Automatic Resolution of Pipeline Hazards in Pipeline Synthesis of Instruction Set Processors by Ing-Jer Huang and Alvin M. Despain |
| CENG 93-22 | Advanced Silicon Compiler in Prolog by Iksoo Pyo, Ching-long Su, Ing-jer Huang, Ricky Pan, Youngseon Koh, Hsu-tsun Chen, Gino Cheng, Chi-ying Tsui, and Alvin M. Despain |
| CENG 93-23 | Correctness of a Directory-Based Cache Coherence Protocol: Early Experience by Fong Pong and Michel Dubois |
| CENG 93-24 | BEST: Behavioral Area-Delay Estimator by Kayhan Kucukcakar and Alice C. Parker |
| CENG 93-25 | Data-Driven and Multithreaded Architectures by Jean-Luc Gaudiot and Chinhyun Kim |
| CENG 93-26 | A Symbolic Approach for Checking Functional and Timing by Chih-Tung Chen and Alice C. Parker |
| CENG 93-28 | Hardware/Software Tradeoffs in ADAM by Jagannath Raghavendra and Alice Parker |
| CENG 93-29 | Concurrent High-Level Synthesis with Floorplanning by Jen-Pin Weng |
| CENG 93-30 | Loss Performance & Queue Length Statistics for Multimedia Communication Systems by Shiouming Stanley Wang and John A. Silvester |
| CENG 93-31 | Edge-Valued Binary-Decision Diagrams: Theory and Applications by Yung-Te Lai, Massoud Pedram, and Sastry, Vrudhula |
| CENG 93-32 | Unified System Construction by Alice C. Parker, Chih-Tung Chen & Pravil Gupta |
| CENG 93-33 | A Low Cost BIST Methodology & Associated Novel Test Pattern Generator by Sen Pin Lin, Sandeep K. Gupta and Melvin A. Breuer |
| CENG 93-34 | BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms by Chih-Ang Chen and Sandeep K. Gupta |
| CENG 93-35 | Modelling the Output Process of an ATM Multiplexer with Markov Modulated Arrivals by Nelson Fonseca and John Silvester |
| CENG 93-36 | Estimating End-to-End Delay in ATM Virtual Paths by Estimating End-to-End Delay in ATM Virtual Paths |
| CENG 93-37 | High Level Interprocess Communication Primitives For A Prolog to C-Parallel Translator by Amaury de Cazanove |
| CENG 93-38 | ProPart: A Process-Level Behavioral Partitioner by Chih-Tung Chen and Alice C. Parker |
| CENG 93-39 | SMASH: A Program for Scheduling Memory-Intensive Application Specific Hardware by Pravil Gupta and Alice Parker |
| CENG 93-40 | Fuzzy Communications, Etc by Chien-Ming Cheng and Kai Hwang |
| CENG 93-41 | Compiler-Directed etc. by Chien-Ming Cheng and Kai Hwang |
| CENG 93-42 | Performance Results of The NAS Parallel Benchmarks in SISAL by Hung-Yu Tseng and Jean-Luc Gaudiot |
| CENG 93-43 | Exact & Approximate Methods for Calculating and Transition Probabilities in FSM's by CH-Ying Tsui, Massoud Pedram, Alvin Despain |
| CENG 93-44 | Reduce Power Consumption of a High Performance Processor Through Gray Code Addressing by Ching-Long Su, Chi-Young Tsui, Alvin M. Despain |
| CENG 93-45 | Cold Scheduling: Schedule Instructions for Less Bit Switches by Ching-Long Su and Alvin M. Despain |
| CENG 93-46 | Branch with Masked Squashing in a Superpipelined Prolog Processor by Ching-Long Su and Alvin M. Despain |
| CENG 93-47 | Logic Verification and Synthesis using Function Graphs by Yung-Te Lai |
| CENG 92-01 | Matching Algorithms and Arichitecture in Hierarchical Shared-Memory Multiprocessor (HSM) Systems by Ashfaq Khokhar and Michel Dubois |
| CENG 92-02 | Synthesis of Interconnection Structures for Multi-Chip Designs by Yung-Hua Hung and Alice Parker |
| CENG 92-03 | CSG: Control Path Synthesis in the ADAM System by Jen-Pin Weng and Alice Parker |
| CENG 92-04 | SWiTEST: Program Organization and Manual by Kuen-Jong Lee and Melvin A. Breuer |
| CENG 92-05 | Towards Synthesizing Memory Architecture for Applications- Specific Systems by Pravil Gupta and Alice C. Parker |
| CENG 92-06 | Reliability Evaluation of Fault-Tolerant Computing Systems and Networks by Meera Balakrishnan |
| CENG 92-07 | A Model for the Performance Analysis of Voice/Data ATM Multiplexers by Shiouming Stanley Wang and John A. Silvester |
| CENG 92-08 | A Multiple Class Buffer Priority Algorithm for the Design of B-ISDN Networks by N. Fonseca and J. A. Silvester |
| CENG 92-09 | Test Pattern Generators for Pseudo Exhaustive Two-Pattern Testing by Sandeep Gupta and Chih-Ang Chen |
| CENG 92-10 | An Approach to Path-Splitting in Multipath Networks by Ram Krishnan and John A. Silvester |
| CENG 92-11 | Delayed Consistency and Its Effects on the Miss Rate of Parallel Programs by Michel Dubois, Jin Chin Wang, Luiz, A. Barroso, Kangwoo Lee and Yung-Syau Chen |
| CENG 92-12 | Scalability Problems in Multiprocessors with Private Caches by Michael Dubois, Luiz, Barroso, Yung-Syau Chen and Koray Oner |
| CENG 92-13 | Cache Inclusion and Processor Sampling in Multiprocessor simuations by Jacqueline Chame and Michel Dubois |
| CENG 92-14 | Improving the Performance of Data Caches in Systems with Large Miss Latencies by Koray Oner and Michel Dubois |
| CENG 92-15 | Alphabetic Fanout Optimization by Hirendu Vaishnav and Massoud Pedram |
| CENG 92-16 | Power-Efficient Technology Decomposition and Mapping by Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain |
| CENG 92-17 | BDD-Based Logic Decomposition: Theory and Practice by Yung-Te Lai, Massoud Pedram, Sarma Sastry |
| CENG 92-18 | Hardware/Software Resolutions for Pipeline Hazards in Instruction Set Processors by Ing-Jer Huang and Alvin Despain |
| CENG 92-19 | The Performance of Cache-Coherent Ring-based Multiprocessors by Luiz Andre Barroso and Michel Dubois |
| CENG 92-20 | The Verification of Cache, Coherence Protocols by Fong Pong and Michel Dubois |
| CENG 92-21 | A Fast Performance Model for Real-Time Multimedia Communications by Shiouming Stanley Wang and John A. Silvester |
| CENG 92-22 | High-Level Synthesis with Pin Constraints for Multiple-Chip Designs by Yung-Hua Hung |
| CENG 92-23 | Dream Machine- A Platform for Efficient Implementation of Neural Networks with Abitrarly Complex by Soheil Shams |
| CENG 92-24 | 2D Object Recognition by Adaptive Feature Extraction and Dynamical Link Graph Matching by Kenneth Flaton |
| CENG 92-25 | BIST Test Pattern Generators for Two-Pattern Pseudo-Exhaustive testing by Sandeep K. Gupta and Chih-Ang Chen |
| CENG 91-01 | Unified System Construction by Kayhan Kucukcakar, Alice C. Parker, Shiv Prakash, Jen-Pin Weng |
| CENG 91-02 | Maximal Diagosis for Wiring Networks by Jung-Cheun Lien and Melvin Breuer |
| CENG 91-03 | A Snooping Cache Coherence Protocol for a Ring Connected Multipro by Luiz A. Barroso and Michel Dubois |
| CENG 91-04 | Stochastic Testability Analysis in Homogeneous Circuits by Amitava Majumdar and Sarma Sastry |
| CENG 91-05 | Neural Network Vision Integration Through Cooperative Learning on a Massively Parallel Computer by Scott Toborg and Kai Hwang |
| CENG 91-06 | Fast Synchronization of Large Multiprocessors Using Wired-NOR Barriers and Counting Semaphores by Kai Hwang and Shisheng Shang |
| CENG 91-07 | Mapping Multicomputer Communication Patterns onto Multiprocessors as Message Vectors in Shared Memory by Dhabaleswar K. Panda and Kai Hwang |
| CENG 91-08 | Performance Analysis of a Simulated Orthogonal Multiprocessor by Kai Hwang and Chien-Ming Cheng |
| CENG 91-09 | SIESTA 1.0 User's Manual by Rajesh Gupta |
| CENG 91-09 | Advanced Serial Scan Design for Testability by Rajesh Gupta |
| CENG 91-11 | Heuristic Process Migration for Dynamic Load Balancing in a Message-Passing Multicomputer by Kai Hwang and Jian Xu |
| CENG 91-12 | Analytical Modeling of Shared Block Contention in Cache Coherence Protocols by Jin-Chin Wang |
| CENG 91-13 | Numerical Partial Differential Equtaions Solvers on Variable-grain Data-flow Multiprocess systems by Chih-Ming Lin |
| CENG 91-14 | Delayed Consistencey and Its Effects on the Miss Rate of Parallel Programs by Michael Dubois, Jin-Chin Wang, Luiz A. Barros, Kangwoo Lee, Yung-Syau Chen |
| CENG 91-15 | Reconfigurable Networks For Fast Packet Switching Shih-Chian Yang by Shi-Chian Yang |
| CENG 91-16 | Control Path/Data Path Tradeoffs in VLSI Design by Mitchell J. Misnar |
| CENG 91-17 | A Mathematical Programming Model for Synthesis of Multiprocessor systems: Linearization, An example Model, and Some Tradeoff Studies by Shiv Prakash and Alice C. Parker |
| CENG 91-18 | A Systematic Approach for Designing Testable VLSI Circuits by Sen-Pin Lin, Charles A. Nijinda, and Melvin Breuer |
| CENG 91-19 | Design of Hierarchically Testable and Maintainable Systems by Jung-Cheun Lien |
| CENG 91-20 | Synthesis of Optimal 1-Hot Coded On-chip Controllers for BIST Hardware by D. Mukherjee, C. Nijinda, and M. A. Breuer |
| CENG 91-21 | VHDL2DDS: A VHDL Language to DDS Data Structure Translator by Chih-Tung Chen |
| CENG 91-22 | Switch Level Test Generation for CMOS Circuits by Kuen-Jong Lee |
| CENG 91-23 | Parallel Orientation of Polygonal Parts by Viktor Prasanna and Anil Rao |
| CENG 91-24 | Parallel Processing of Production Systems on Data-Flow Multiprocessors by Andrew Sohn |
| CENG 91-25 | Parallel Algorithms For Automating VLSI Physical Design by Ravikumar P. Chennagiri |
| CENG 91-26 | Software Aspects of Bold A System and User's Manual by Jung-Cheun Lien |
| CENG 91-27 | System-Level Synthesis Techniques with Emphasis On Partitioning And Design Planning by Kayhan Kucukcakar |
| CENG 91-28 | Numerical Partial Differential Equations Solvers on Variable-grain Data-flow Multiprocessor Systems by Chih-Ming Lin |
| CENG 91-29 | SOS: Synthesis of Application-Specific Heterogeneous Multiprocessor systems by Shiv Prakash and Alice C. Parker |
| CENG 91-30 | Symbolic Jacobian Inversion for Redundant Manipulators by Carlos L. Luck and Sukhan Lee |
| CENG 91-31 | Emulating a Data-Flow Machine Using a Network of Transputers by Moez Ayed and Jean-Luc Gaudiot |
| CENG 90-01 | SNAP Controller by Hirendu Vaishnav |
| CENG 90-02 | Algorithm-Driven Performance Simulation of the USC Orthogonal Multiprocessor by Chien-Ming Cheng, Sharad Mahrotra, Michael Dubois, Kai Hwang |
| CENG 90-03 | Architectural Design of the USC Orthogonal Multiprocessor by K. Hwang, D. K. Panda, S. Rao and H. Nais |
| CENG 90-04 | The USC Orthogonal Multiprocessor for Image Processing with Neural Networks by K. Hwang D. K Panda, N. Haddadi and R. Chellappa |
| CENG 90-05 | A Decoupled Graph/Computation Architecture with Variable Resolution Actors by P. Evripidou and Jean-Luc Gaudiot |
| CENG 90-06 | Dynamic Routing and Congestion Control for Multi-Class Virtual Circuit Networks by A. A. Eonomides, P. A. Ioannou and J A. Silvester |
| CENG 90-07 | Evaluating Optimizing Transformations of Behavioral Descriptions by Rajiv Jain and Alice Parker |
| CENG 90-08 | Test Generation for the JPL Viterbi Decoder Chip by M.A Breuer, Margaret Driscoll, Rajesh Gupta, Rajiv Gupta, Shen Lin and Rajagopalan Srinivasan |
| CENG 90-09 | Assigning Signa flow Directions to MOS Transistors by Lee, Gupta, Breuer |
| CENG 90-10 | Test-Efficiency Analysis of Random Self-test of Sequential Circuits by Sastry and Majumdar |
| CENG 90-11 | Stochastic Characterization of Controllability ingeneral NAND and AND Trees by Amita Majumdar and Sharma Sastry |
| CENG 90-13 | Efficient Testing of Acyclic Structures in Partial Scan Designs by Rajesh Gupta and Melvin A. Breuer |
| CENG 90-14 | A Module Maintenance Controller Prototype by Jung-Chuen Lien |
| CENG 90-15 | Asynchronous Iterative Algorithms for Problems with Discrete Data by Aydin Uresin |
| CENG 90-16 | Priority Load Sharing: An Approach Using Stackelberg Games by A. A. Economedies and John Silvester |
| CENG 90-17 | VYUHA: A Detailed Router for Multiple Routing Models by C.P. RaviKumar and S. Sastry |
| CENG 90-18 | Virtual Address Caches by Michael Cekleov, Michael Dubois, Jun-Chin Wang, Faye A. Briggs |
| CENG 90-19 | A Methodology for Partitioning and Hierarchical Reorganization of Ssequential Circuits for DFT and BIST by Rajiv Gupta, Rajagopalan Srinivasan and Melvin Breuer |
| CENG 90-20 | On Optimal and Practical Routing Methods for a Massive Data Movement Operation on Hypercubes by Rajendra V. Boppana and C. S. Raghavendra |
| CENG 90-21 | Delayed Consistency Protocols by Michael Dubois |
| CENG 90-22 | Improving Structure Handling and Recursive Function Calls in the USC Occamflow Translator by Jean-Pierre Abello |
| CENG 90-23 | Macro Data-Flow Simulator Display Interface by Olivier Tardieu |
| CENG 90-24 | The Effects of Physical Design Characteristics on the Quality of Synthesized Designs by Alice C. Parker, Jen-Pin Weng, Pravil Gupta and Agha Hussain |
| CENG 90-25 | Synthesis of Application-Specific Multiprocessor Architectures by Shiv Prakash and Alice C. Parker |
| CENG 90-26 | CHOP: A Constraint-Driven System- Level Partitioner by Kayhan Kucukcakar and Alice .C Parker |
| CENG 90-27 | 3D Scheduling: High Level Synthesis with Floorplanning by Jen-Pin Weng and Alice C. Parker |
| CENG 90-28 | Reconfigurable fault Tolerant Networks for Fast Packet Switching by Shih-Chian Yang and John A. Silvester |
| CENG 90-29 | The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve by Alice Parker, Pravil Gupta and Agha Hussain |
| CENG 90-30 | Flexible, Fault-Tolerant Routing Criteria for Circuit-Switched Hypercubes by Ge-Ming Chiu, Suresh Chalasani and C.S. Raghavandra |
| CENG 90-31 | BAD: Behavioral Area-Delay Predictor by Kayhan Kucukcakar and Alice C. Parker |
| CENG 90-32 | The Synthesis of Control-Dominated Application Specific Integrated Circuits Using Global Based Design Management by Sally Hayati |
| CENG 89-01 | Fault Tolerance and Reliability Analysis of Large-Scale Multicomputer Systems by Walid A. Najjar |
| CENG 89-02 | Parallel Computing with Optical Interconnects by Mehrnoosh Mary Eshaghian |
| CENG 89-03 | Test Generation Systems (TGS) User's Manual-Version 1.0 by Kuen-Jong Lee |
| CENG 89-05 | Detailed Analysis of Bridging Faults in CMOS Scan Registers by Kuen-Jong Lee and Melvin A. Breuer |
| CENG 89-06 | The EVE VLSI Management Environment by Hamiden Afsarmanesh, Esther Brotoatmodjo, Kwang June Byeon and Alice Parker |
| CENG -89-07 | LARA: A Layout Accelerator based on Reduced Array Architecture by C. P. RaviKumar and Sarma Sastry |
| CENG -89-09 | A Parallel Approach to Three-Layer Channel Routing by C. P. RaviKumar and Sarma Sastry |
| CENG 89-10 | SNAP: A Marker-Propagation Architecture for Knowledge Processing by Dan Moldovan, Wing Lee, Changhwa Lin |
| CENG 89-11 | SNAP: Simulation Results by Dan Moldovan, Changhwa Lin |
| CENG 89-12 | Text Understanding on SNAP by Dan Moldovan and Ig-Tae Um |
| CENG 89-13 | Reasoning on the Connection Machine by Sang-Hwa Chung and Dan Moldovan |
| CENG 89-14 | Control in Productions Systems with Multiple rule Firings by Moldovan, Kuo and Cha, Steve Kuo, Dan Moldovan and Urula Schwultke |
| CENG 89-15 | Parallel Asynchronous Algorithms for Discrete Data by Michael Dubois and Adsin Uresin |
| CENG 89-16 | An Asynchronous All Pairs Shortes Path Algorithm for Multiprocessors by Uresin and Dubois |
| CENG 89-17 | Worst Case Analysis of Asynchronous Iterative Algorithms by Uresin and Dubois |
| CENG 89-18 | Analytical Modeling of Data Sharing in Cache-Based Multiprocessors by Wang and Dubois |
| CENG 89-19 | Access Ordering and Coherence in shared Memory Multiprocessors by Scheurich |
| CENG 89-20 | Asynchronous Iterations with Bonded Delay by Uresin and Dubois |
| CENG 89-21 | Data Path Design Tradeoffs Using MABAL by Kayhan Kucukcakar and Alice C. Parker |
| CENG 89-22 | Fault Tolerant Multistage Interconnection Networks by Yang and Silvester |
| CENG 89-23 | High-Level Area Delay Prediction with Application to Behavioral Synthesis by Rajiv Jain |
| CENG 89-24 | Bandwidth Analysis of Message-Passing Networks by Moldovan |
| CENG 89-25 | Queueing Analysis of an ATM Switch with Multichannel Transmission by Arthur Lin and John Silvester |
| CENG 89-26 | Fixed-Node Routing and Architecture and its Performance in an ATM Switch by Arthur Lin and John Silvester |
| CENG 89-27 | The Macro Data Flow Simulator by Namhoon Yoo and Jean-Luc Gaudiot |
| CENG 89-28 | The USC Macro Data-Flow Assembly Language by Jean-Luc gaudiot and Moez Ayed |
| CENG 89-29 | The State of the Art in Parallel Production Systems by Steven Kuo and Dan Moldovan |
| CENG 89-30 | Implementation of Neural Networks on Massive Memory Organizations by Manavendra Misra and V.K. Prasanna Kumar |
| CENG 89-31 | Architecture Embeddings Designs a Simulation of an i860 Based Orthogonal Multiprocessor by K. Hwang, D. Panda, C. Ching, S. Rao, S. Mahotra, H. Nair |
| CENG 89-32 | Representing Temporal Information for Digital System Software by John Granacki and Alice Parker |
| CENG 89-33 | The Design of the SNAP Chip by Wing Lee and Dan Moldovan |
| CENG 89-34 | Parallel Classification for Knowledge Representation on SNAP by Juntae Kim and Dan Moldovan |
| CENG 89-35 | The Performance of an ATM Switch with Multichannel Transmission groups by Arthur Lin and John Silvester |
| CENG 89-36 | Self Routing Schemes in Parallel Memory Access by Boppana and Raghavendra |
| CENG 89-37 | Optimal Self Routing of Linear-Complement Permutations in Hypercubes by Boppana and Raghavendra |
| CENG 89-38 | Routing Games by A. A. Economides and John Silvester |
| CENG 89-39 | Priority Load Sharing: An Approach Using Stackalberg Games by A.A. Economides and J.A. Silvester |
| CRI-88-01 | Towards a Unified Decision Technology: Area of Common Interest through Artificial intelligence and Business Forecasting by Bruce Abramson |
| CRI-88-02 | Object Flavor Evolution in an Object Oriented Database System by Qing Li, Dennis McLeod |
| CRI-88-03 | Conceptual Database Evolution through Learning by Qing Li, Dennis McLeod |
| CRI-88-04 | On-Chip Controller Design for Built-in-Text by Melvin Breuer |
| CRI-88-05 | Parallel Asynchronous Algorithms for Discrete Data by Majid Haghoo, Wlodek Proskurowski |
| CRI-88-06 | Parallel efficiency of a Domain Decomposition Method by Majid Haghoo, Wlodek Proskurowski |
| CRI-88-07 | Object Database Support for a Software Project Management Environment by Lung-Chun Liu, Ellis Horowitz |
| CRI-88-08 | On the Composition of Datalog Program Mapping by Guozhu Dong |
| CRI-88-09 | Dual Redundant Arm Configuration Optimization with Task-Oriented by Sukhan Lee, Jang M. Lee |
| CRI-88-10 | Variable-Axis Tool Positioning for NC Path Generation by Allan Hansen, Farhad Arbab |
| CRI-88-11 | The ADAM Design Planning Engine by David W. Knapp, Alice C. Parker |
| CRI-88-12 | Data Path Synthesis of Pipelined Designs: Theoretical Foundations by R. Jain, N. Park, A. C. Parker |
| CRI-88-13 | Multi-Agent Cooperative Problem Solving and Learning with Axiom-Based Reasoning by Sukhan Lee, Yeong Gil Shin |
| CRI-88-14 | Optical Communication for Pointer-Based Algorithms by Richard J. Anderson, Gary L. Miller |
| CRI-88-15 | P3: A Parallel Planner Concurrently Generating Parallel Plans by Sukhan Lee, Kyusik Chung |
| CRI-88-16 | Multilayer Feedforward Potential Function Network by Sukhan Lee, Rhee M. Kil |
| CRI-88-17 | Sequential and Parallel Algorithms for Computing a Large Independent Set in Planar Graphs by M. Chrobak. J. Naor |
| CRI-88-18 | Fairness Considerations in an Integrated Voice/Data LAN by C. Yuan, J. Silvester |
| CRI-88-19 | Numerical Algoriths in a Data-Driven Environment by J.-L. Gaudiot, P. Evripidou |
| CRI-88-20 | Minimum Spanning Tree on the HMESH Architecture by R. V. Boppana, C. S Raghavendra |
| CRI-88-21 | Fault-tolerant Networks based on the de Brujin Graph by M. A. Sridhar, C. S. Raghavendra |
| CRI-88-22 | A New approach to the Rearrangeability Problem of Multistage Interconnection Networks by C. S. Raghavendra, M. A. Sridhar, Suresh Chalasani |
| CRI-88-23 | Minimal Full-Access Networks; Enumeration and Characterization by M. A. Sridhar, C. S. Raghavendra |
| CRI-88-24 | Programming INMOS Transputers in a High-Level Data-Flow Language by J. L. Gaudiot, T. L. Lee |
| CRI-88-25 | Queueing Analysis of Delay Constrained Voice Traffic in a Packet Switching System by Chin Yuan, John A. Silvester |
| CRI-88-26 | Shared Data Contention in a Cache-Coherence Protocol by M. Dubois, J.-C. Wong |
| CRI-88-27 | An Area-Time Model for Synthesis of Non-Pipelined Designs by R. Jain, M. J. Mlinar, A. C. Parker |
| CRI-88-28 | Representation of Control in timing Behavior with Applications to Interface Synthesis by S. Hayati, A. Parker |
| CRI-88-29 | Concurrent Lisp Execution of AI-Oriented Gabriel Benchmarks with Hybrid Load Balancing by Raymond Chowkwanyun, Kai Hwang |
| CRI-88-30 | Analysis of Memory Access Dependencies in Shared-Memory Multiprocessors by M. Dubois, C. Scheurich |
| CRI-88-31 | Examples of Geometric Reasoning by F. Arbab |
| CRI-88-32 | by Prasanna Kumar |
| CRI-88-43 | Dynamic Load Balancing in Distributed Heterogeneous Computer Systems by Tze-Hore Howard Liu |
| CRI-88-59 | A Methodology for Partial Scan Design Using Balanced Sequential Structures by Rajesh, Rajiv Gupta and Melvin Breuer |
| CRI-88-60 | On the Performance of Protocols to Support Intergrated Voice and Data Services by Chin Yuan and John Silvester |
| CRI-88-61 | MABAL: A Software Package for Module and Bus ALlocation by Kayhan Küçükçakar and Alice C. Parker |
| CRI-88-62 | Detecting Multiple Bridging Faults in CMOS Combinational Circuits by Kuen-Jong Lee and Melvin Breuer |
| CRI-87-01 | MACE: A FlexibleTestbed for Distributed AI Research by L. Gasser, C. Braganza, N. Herman |
| CRI-87-02 | Understanding Digital System Specifications Written in Natural Language by J.J. Granacki, Jr. |
| CRI-87-03 | Hypernets for Parallel Processing with Connectionist Architectures by K. Hwang, J. Ghosh |
| CRI-87-04 | Dynamic Load Balancing Methods for Message-Passage Multicomputers by K. Hwang, R. Chowkwanyun |
| CRI-87-05 | An Orthogonal Multiprocessor for Efficient Parallel Processing by K. Hwang, P.S. Tseng, D. Kim |
| CRI-87-06 | A Planning Model of the Design Process by D.W. Knapp |
| CRI-87-07 | Multiple Agent Cooperative Problem Solving with Axiom-Based Negotiation by Sukhan Lee, Yeong Gil Shin |
| CRI-87-08 | Interconnection Protocols for Interorganization Networks by D. Estrin |
| CRI-87-09 | Predicting Area Time Trade Offs Pipeline Designs by R. Jain, A. Parker, N. Park |
| CRI-87-10 | REAL: A Program for Register Allocation by F.J. Kurdahi, A.C. Parker |
| CRI-87-11 | PHRAN-SPAN; A Natural Language Interface for System Specifications by J.J. Granacki, A.C Parker |
| CRI-87-12 | Molecules: A Language Construct for Concurrent Programming by Z. Xu, K. Hwang |
| CRI-87-13 | Built-in Test for Folded Programmable Logic Arrays by M.A. Breur, F. Saheban |
| CRI-87-14 | Self-Diagnosis of Regular Arrays of Processors by F. Saheban, M.A. Breur |
| CRI-87-15 | Pipeline Nets for Compound Vector Supercomputing by K. Hwang, Z. Xu |
| CRI-87-16 | MACE: Multi-Agent Computing Environment Version 6.0 Release Note by C. Braganza, L. Gasser |
| CRI-87-17 | Dynamic Parallel Complexity of Computational Circuits by G. Miller, S.H. Teng |
| CRI-87-18 | Parallel Tree Contraction Part I- Fundamentals by G. Miller, J.H. Reif |
| CRI-87-19 | Minimal State Space Search in Production Systems by D. Moldovan, V. Dixit |
| CRI-87-20 | Schematic Database Modelling: Survey, Applications and Research Issues by R. Hull, R. King |
| CRI-87-21 | Fixed Axis Tool Positioning with Built in Global Interference Checking for NC-Path Generation by A. Hansen, F. Arbab |
| CRI-87-22 | Advanced Parallel Processing and Supercomputer Architectures by K. Hwang |
| CRI-87-23 | Minimal Full-Access Networks; Enumeration and Characterization by M. A. Sridhar, C. S. Raghavendra |
| CRI-87-24 | Proposal for an Integrated System for Software Project Management by E. Horowitz |
| CRI-87-25 | An Extensible Object-Oriented Framework for Engineering Design by K.V. Bapa Rao |
| CRI-87-26 | Parallel Tree Contraction Part 2: Further Applications by G. Miller, J.H. Reif |
| CRI-87-27 | A Paradigm for Intelligent CAD for Inter-Organization Networks by F. Arbab |
| CRI-87-28 | Interconnection Protocols for Inter-Organization Networks by D. Estrin |
| CRI-87-29 | Interconnection of Private Networks: A Like Between Industrial and Telecommunications Policy by D. Estrin |
| CRI-87-30 | Detection of CMOS Stuck- Open Faults Using Random and Pseudo-Random Test Sequences by S. Sastry, M. Breuer |
| CRI-87-31 | Multi-Robot Assembly Process Planning by S. Lee, Y.G. Shin |
| CRI-87-32 | RUBIC: A Multiprocessor for Rule-Based Systems by D. Moldovan |
| CRI-87-33 | The Control of Surface Contact and Slide Using Wrist Force/Torque Sensor by S. Lee, J.M. Lee |
| CRI-87-34 | Optimal Allocation of Tasks to Multiprocessors by D. Moldovan, R. Ashvin |
| CRI-87-35 | Parallelism Analysis in Rule-Based Systems using Graph Grammars by D. Moldovan, F. Parisi-Presicce |
| CRI-87-36 | The Allocation Problem in Parallel Production Systems by V. Dixit, D. Moldovan |
| CRI-87-37 | Para-Logic Programming: A Technique for Developing Parallel Programs by D. Jacobs |
| CRI-87-38 | Analysis and Algorithms for the Area Efficient Layout of Custom Integrated Circuits by M.S. Chandrasekhar |
| CRI-87-39 | A Distributed-Control Function Invocation Mechanism for Data-Driven Execution by Y. H. Wei, J-L. Gaudiot |
| CRI-87-40 | Area Estimation of VLSI Circuits by F. Kurdahi |
| CRI-87-41 | A formal model for software project management by L.C. Liu, E. Horowitz |
| CRI-87-42 | A Simple Proof of Rearrangeability of Five Stage Shuffle/Exchange Network for N=8 by K. Kim, V.K. Prasanna Kumar |
| CRI-87-43 | On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication by Tsai, V.K. Prasanna Kumar |
| CRI-87-44 | An Efficient Fixed Size Array for Solving Large Scale Toepliz Systems by A. Daghi, V.K. Prasanna Kumar, A. Safari |
| CRI-87-45 | by S. Kurtzman, S. Ginsburg |
| CRI-87-46 | Input Dependent only Object Histories by S. Ginsburg, D. Tiang |
| CRI-87-47 | Sense & Verifiable Schemes for Electron & General Distributed Computing Problems by M-D. Huang, S-H. Teng |
| CRI-87-48 | VLSI Arrays with Reconfigurable Buses (Preliminary Version) by V.K. Prasanna Kumar, D. Reisis |
| CRI-87-49 | A Reduced Mesh of Trees Organization for Efficient Solutions to Graph Problems by V.K. Prasanna Kumar, H.M. Alnuweiri |
| CRI-87-50 | by V.K. Prasanna Kumar, H.M. Alnuweiri |
| CRI-87-51 | Multiprocessor of Functions for Concurrent Lisp Processing by K. Hwang, R. Chowkwanyun |
| CRI-87-52 | Design and Analysis of Reliable Interconnection Networks by A.M. Varma |
| CRI-87-53 | Optimal Tree Contraction in EREW Model by H. Gazit, G.L. Miller, S.H. Teng |
| CRI-87-54 | A Parallel Algorithm for Finding a Separator in Planar Graphs by H. Gazit, G. L. Miller |
| CRI-87-55 | A Two-mode Dynamic Algorithm (TMDA) for Load-Balancing in Distributed Systems by H. T. Liu, J. A. Silvester |
| CRI-87-56 | Managing the Components of a Large-Scale Software Systems by Y. Sugiyama, E. Horowitz |
| CRI-87-57 | Fixed-Axis Tool Positioning with Built-in Global Interference Checking for NC Path Generation by A. Hansen, F. Arbab |
| CRI-87-58 | Contemporary Tool Positioning Methods by |
| CRI-87-59 | Module Selection for Pipelined Design by R. Jain, A. Parker, N. Park |
| CRI-87-60 | Understanding Software Documentation: Product Processes and Settings by A. Jazzar |
| CRI-87-61 | by K. Hwang, H. C. Wang |
| CRI-87-62 | Demand-driven Interpretation of FP programs on a Data-Flow Multiprocessor by J.-L Gaudiot, Y. H. Wei |
| CRI-87-63 | Remarks on Spectroequivalence of Certain Discreet Operators by Wlodek Proskurowski |
| CRI-87-65 | Mapping Neural Networks onto Highly Parallel Multiprocessors by Joydeep Ghosh, Kai Hwang |
| CRI-87-65 | Understanding Software Technology Transfer by Walt Scacchi, Jimm Babcock |
| CRI-87-66 | Understanding Software Technology Transfer by Walt Scacchi, Jimm Babcock |
| CRI-87-67 | Understanding Software Productivity by Walt Scacchi, C. M. K. Kintala |
| CRI-87-68 | The USC System Factory Project by Walt Scacchi |
| CRI-87-69 | Understanding Software Documentation: Products Processes and Settings by Abdulaziz Jazzar, Walt Scacchi |
| CRI-87-70 | Understanding the Production and Consumption of Software Documentation: An Empirical Study and Model by Abdulaziz Jazzar |
| CRI-87-71 | Abstraction Mechanism in Hypertext by Pankaj K. Garg |
| CRI-87-72 | A Hypertext System to Manage Software Life Cycle Documents by Pankaj K. Garg, Walt Scacchi |
| CRI-87-73 | A Software Hypertext Environment for Configured Software Descriptions by Pankaj K. Garg, Walt Scacchi |
| CRI-87-74 | On Designing Intelligent Hypertext Systems for Information Management in Software Engineering by Pankaj K. Garg, Walt Scacchi |
| CRI-86-01 | On Mapping Parallel Algorithms Into Mesh-Connected Computers by T.C. Lin, D.I. Moldovan |
| CRI-86-02 | Supercomputers and Artificial Intelligence Machines by K. Hwang, J. Ghosh |
| CRI-86-03 | Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks by C.S. Raghavendra, A. Varma |
| CRI-86-04 | Rearrangeability of Multistage Shuffle/Exchange Networks by C.S Raghavendra, A. Varma |
| CRI-86-05 | Rearrangeability of the 5-Stage Shuffle/Exchange Network for N=8 by C.S Raghavendra, A. Varma |
| CRI-86-06 | Fault-Tolerant Routing in Multistage Interconnection Networks by A. Varma, C.S Raghavendra |
| CRI-86-07 | Reservation CSMA/CD: A New Multiple Access Protocol For Lan by S.J.Chen, Victor O.K. Li |
| CRI-86-08 | A Termination Protocol For Simple Network Partitioning in Distributed Database Systems by C.L. Huang, V.O.K. Li |
| CRI-86-09 | Token Relabeling in a tagged data-flow architecture by J.L. Gaudiot, Y.H. Wei |
| CRI-86-10 | Iterative methods in subspace for solving elliptic problems using domain decomposition by M. Dryja, W. Proskurowski |
| CRI-86-11 | A knowledge based system for designing testable VLSI circuits by M. S. Abadir |
| CRI-86-12 | Domain decomposition seminar notes by M. Dryja, W. Proskurowski |
| CRI-86-13 | Parallel Processing Model for Loging Programming by Y-W. Tung |
| CRI-86-14 | Parallel I/O Processing in High-Speed Finite-Element Multiprocessors by K. Hwang, P. Tseng |
| CRI-86-15 | Reliability Analysis and Optimization the Design of Distributed Systems by S. Hariri |
| CRI-86-16 | Pyramids versus Enhanced Arrays for Parallel Image Processing by V. K. P. Kumar, D. Reisis |
| CRI-86-17 | Computer Architectures for Artificial Intelligence Processing by K. Hwang, J. Ghosh, R. Chowkwanyun |
| CRI-86-18 | Mapping Algorithms into Mesh Connected Computers by T.C. Lin, D.I. Moldovan |
| CRI-86-19 | Power and Ground Routing for Semi-Custom VLSI Circuits by S. Chowdhury |
| CRI-86-20 | Dependancy and Hazard Resolution in Multiprocessors by M. Dubois, C. Scheurich |
| CRI-86-21 | Performance Optimization Techniques for an Object-Oriented Semantic Data Model by R. Ahad, D. McLeod |
| CRI-86-22 | Synchronization, Coherence and Ordering of Events in Multiprocessors by M. Dubois, C. Scheurich, F.A. Briggs |
| CRI-86-22 | A Knowledge Based System for Testable Design Methodology Selection by Xi-an Zhu |
| CRI-86-26 | Molecules: Typed Procedures for Concurrent Programming on Vector/Parallel and Distrbuted Computers by Z. Xu, K. Hwang |
| CRI-86-27 | Application of Analytical Program Models to the Evaluation of Cache-Based Systems by M. Dubois, J.C. Wang |
| CRI-86-28 | Efficient Parallel Algorithms for Image Template Matching on Hyercube SIMD Machines by V.K.P Kumar, V. Krishnan |
| CRI-86-29 | Reduced Model Adaptive Inverse Control for Accurate Robot Arm Path Tracking by S. Lee |
| CRI-86-30 | Expert Assisted Robot Skill Acquisition Part I: Theory and Skill Transfer by S. Lee, M-H. Kim |
| CRI-86-31 | Expert Assisted Robot Skill Acquisition Part II: Skill Discovery and Experimentations by S. Lee, M-H. Kim |
| CRI-86-32 | Efficient Parallel Evaluation of Straight-Line Code and Arithmetic Circuits by G. Miller, V. Ramachandran, E. Kaltofen |
| CRI-86-35 | VTRAN: A VT to PNF Translator by M. Milnar, A. Parker |
| CRI-86-37 | Numerical Experiments and Implementation of a Domain Decomposition Method with Cross Points for the Model Problem by M. Dryza, W. Proskurowski, O. Widlund |
| CRI-86-38 | A New Dynamic Resource Allocation Scheme for Distributed Computer Systems by H. Liu, J. Silvester |
| CRI-85-02 | DIP A Data-Driven Instruction Pipeline Architecture by M. Dubois, C. Schewrich |
| CRI-85-05 | Area Estimation of VLSI Integrated Circuits by Fadi J. Kurdahi and Alice c. Parker |
| CRI-85-07 | A Reduced Multiprocessor for VLSI Implementation of Parallel Algorithms by K. Hwang, P.S Tseng |
| CRI-85-08 | Multipipeline Networking for Fast Evaluation of Vector Compound Functions by K. Hwang, Z. Xu |
| CRI-85-09 (DISC/85-3) | An Extensible Object-Oriented Approach to Databases for VLSI/CAD by Hamideh Afsarmanesh, Dennis McLeof, David Knapp and Alice Parker |
| CRI-85-11 | An Approah to Semi-Automatic Physical Database Design and Evolution for Personal Information Systems by Rafiul Ahad and Dennis McLeod |
| CRI-85-13 | The Relation-Partitioning Approach to Processing Star Queries in Distributed Databases by C. P. Wang, Victor O.K. Li |
| CRI-85-16 | Geometric Reasoning: A New Paradigm for Processing Geometric Information by F. Arbab, J. Wing |
| CRI-85-16 (DISC 83-6a) | A Data Structure For VLSI Synthesis and Verification by David W. Knapp and Alice C. Parker |
| CRI-85-21 | The 3DIS: An Extensible Object-Oriented Framework for Information Managementon by Hamideh Afsarmanesh Tehrani |
| CRI-85-22 | 3.3 Interface and I/O Protocal Descriptions by Alice C. Parker and Nohbyung Park |
| CRI-85-23 | Synthesis of High-Speed Digital Systems by Nohbyung Park |
| CRI-85-25 | A Design Utility Manager by David W. Knapp and Alice C. Parker |
| CRI-85-28 | The Effect of Register-Transfer Design Tradeoffs on CHIP Area and Performance by John J. Granacki and Alice C. Parker |
| CRI-85-29 | Simulation Effectiveness Research Report by John J. Granacki and Alice C. Parker |
| CRI-85-30 | Wiring Space Estimation of Master Slice ICS by Sarma Sastry |
| CRI-85-31 | On the Relation between Wire Length Distributions and Placement of Logic on Master Slice ICS by Sarma Sastry |
| CRI-85-32 | Synthesis of Optimal Clocking Schemes for Digital Systems by Nohbyung Park and Alice C. Parker |
| CRI-85-33 | Simulation Effectiveness and Design Verification (Final Report) by Alice C. Parker, Nohbyung Park and David W. Knapp |
| CRI-85-34 | The ADAM Advanced Aotomation System: Overview, Planner and Natural Language Interface by John Granacki, David Knapp and Alice Parker |
| CRI-85-36 | Synthesis of Optimal Pipeline Clocking Schemes Nohbyung Park and Alice Parker |
| CRI-85-37 | FLEXISM: A Simulation Environment for Multiprocessor Systems by J.Y.J. Liang, M. Dubois |
| CRI-85-38 | Trace Driven Simulations of Parallel, Distributed Algorithms in Multiprocessors by M. Dubois, J.L. Gaudiot, N. Tohme |
| CRI-85-39 | Analysis of Partitioning and Allocation Techniques in a Cluster-Based Machine by M. Dubois, J.L. Gaudiot, N. Tohme |
| DISC/84-3 | The VLSI Implementation of A Square Root Algorithm by J. Bannur and A. Varma |
| DISC/83-1 | Roving Emulations as Applied to a (255, 223) RS Encoder System by M.A. Breuer, F. Cohen, and A.A. Ismaeel |
| DISC/83-2 | Simulation Effectiveness Research Report by Alice C. Parker |
| DISC/83-3 | RC Synthesis VLSI Macrocelis by Davis Knapp and Melvin A. Breuer |
| DISC/83-4 | ART: A high Level Layout Specification Language by D.W. Knapp |
| DISC/82-5 | On Area and Yield Considerations For Fault-Tolerant VLSI Processor Array by Isreal Koren and Melvin A. Breuer |
| DISC/82-6 | The Automatic Design of Testable Circuits by M.A. Breuer |
| DISC/82-7 | A Placement Algorithm For Array Processors by Dah-juh Chyan and Melvin A. Breuer |
| DISC/82-8 | The USC Roving Emulator by Fred Cohen |
| DISC/82-9 | Error Detection in Sequential Circuits Using Roving Emulations As a Detection Mechanism by Asad A. Ismaeel |
| DISC/82-10 | The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance by John J. Granacki and Alice Parker |
| DISC/81-1 | A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array by Isreal Koren |
| DISC/81-2 | Optimized Unidirectional Routing by Hyeran Jeon, Gabriel H. Loh, Murali Annavaram |
| DISC/81-3 | Theoretical Aspects of the Behavior of Digital Circuits Under Random Inputs by S.K Kumar |
| DISC/81-4 | Easily Testable Bit-sliced Digital Systems by T. Sridhar |
| USCEE No. 510 | Fault Tolerence of β-Networks in Interconnected Multicomputer Systems by John P. Shen |