Thursday, August 20, 2020
- Registration for this online exam is for On-campus and DEN students.
- Register by Friday, August 14.
- Must have a desktop computer or laptop with a webcam for proctoring and monitoring purposes. A few days before the exam, we will set up a sample quiz for students can take to prepare for the exam. This sample quiz will have a Lockdown Browser enabled by itself or Lockdown plus Monitor tool together.
- All exams are approximately 60 minutes and will begin promptly at the designated start time.
- You may use a pencil with an eraser. Technically, students can use a blank sheet of paper during the tests for math-related problems. Specific details will be provided during the sample quiz.
- No calculators will be allowed.
- Must show your USC ID card for identification purposes. *Note: If you do not have a USC ID card yet, you may use your driver’s license or a passport photo page during the identification process.
The times listed below are all US-Pacific time. All times are subject to change. We will update this site again before August.
EE 450: 10 a.m. - 11:30 a.m.
EE 457: 1 p.m. - 2:30 p.m.
EE 477: 3 p.m. - 4:30 p.m.
We will no longer offer EE-479 as a placement exam. You will be able to login to http://myviterbi.usc.edu and view your results the following week.
Once you have passed the necessary placement tests for a higher-level course, you will be able to register for that course for any future semester.
Passing a placement exam fulfills pre-requisites for taking 500/600-level graduate classes, but it does not automatically satisfy course requirements and graduate credit for specific degree programs, if any.
EE 450: Introduction to Computer Networks
Computer Networks by Peterson
Data & Computer Communication by Stallings
Computer Networks by Tannenbaum
Communications networks and services, classifications of networks, performance measures such as Throughput and Delay. The public Internet and PSTN. Convergence of services. Networking topologies.
Network layered architecture, protocols and interfaces. OSI model, TCP/IP model, two- and three-tier client-server models, peer-process communications
Data communications: Analog and digital signaling, sampling theorem, data and signaling rates, modems, time division and statistical multiplexing, link capacity, transmission media, line coding.
Link layer Procedures: Error detection and control, flow control, sliding window procedures. Examples of link protocols including PPP and HDLC.
Local Area Networks: Ethernet, Token rings and wireless LANs. Media access control procedures, CSMA/CD, Token Passing and CSMA/CA. Shared vs. switched LANs. LAN hardware and software components. LAN performance analysis
TCP/IP and the Internet: The Internet Protocol, packet format, IP addressing and subnetting, fragmentation and re-assembly, address resolution protocol, routing and forwarding tables, routing algorithms (RIP, OSPF and BGP), transport layer protocols, TCP and UDP, connection establishment, end-to-end flow and error control procedures, advertised windows, slow-start, long-fat networks, congestion control, port and socket addressing, etc…
Watch online modules of EE-450 concepts below:
EE457: Computer Systems Organization
Textbook: Computer Organization & Design - The Hardware and Software Interface (2nd edition) by D. A. Patterson (Berkeley) and J. L. Hennessey (Stanford)
EE102L review: Basic digital system design -- Datapath unit design and Control unit design
Basic concepts of assembly language, unsigned and signed numbers, Booth's multiplication and restoring and non-restoring division algorithms.
CPU performance: relation between execution time of a program and the CPU specs (instruction count, clocks per instruction, and clock period).
Compare and contrast CISC and RISC instruction sets, simple ALU design, CLA (carry look-ahead adder), CSA (carry save adder) and application to multiplication.
CPU design: Single cycle CPU design, multi-cycle CPU design, pipelined CPU design including dependencies, hazard detection, stalling, forwarding, branching, flushing, branch penalty due to flushing, branch delay slots.
Memory and cache organization: fully associative, direct, and set associative mappings, cache TAG RAMs, and cache DATA RAMs, interleaved main memory to facilitate fast block transfer between main memory.
Virtual memory: page tables (single-level, multi-level), TLBs, introduction to multiprocessors, cache coherency (MESI protocol).
EE 477: MOS VLSI Circuit Design
Recommended Textbook: Principles of CMOS VLSI Design by Weste and Eshroghian
Analysis and design of digital MOS VLSI circuits including area, delay and power minimization. Laboratory assignments including design, layout, extraction, simulation and automatic synthesis.
Static characteristics: structure and (V-I) characteristics of MOSFETs, operation as a switch (including weak values), example CMOS and pass transistor circuits, static characteristics of CMOS and pseudo-nMOS inverters.
Layout preliminaries: Introduction to semiconductor processing, layout, and design rules.
Parasitics and performance: Estimation of parasitics from layout, analytical as well as empirical delay models for gates, wires, and pass transistors. Estimation of power dissipation.
Design of complementary CMOS, pass-transistor and dynamic logic circuits.
Design optimizations: Preferred gate types for various logic styles; buffer design for high fan-out, buffering long wires; transistor level optimizations --- body effect, charge sharing, diffusion capacitance minimization, and transistor sizing; custom layout optimization.
Clocking; latch and flip-flop designs, clocking strategies.