Placement Exams

Spring 2025
**Thursday, January 9, 2025**
Online Exams

Register for placement exams or view your results.

• Registration for this optional online exam is for On-campus and DEN students.
• Register by **January 7, 2025** at the latest on myviterbi.usc.edu or click the register tab above.
• Must have a desktop computer or laptop with a webcam and Zoom for proctoring and identification purposes.  At least a few days before the exam, we will set up a Sample Quiz for students to take to prepare for the exam.  This sample quiz will have a Lockdown Browser enabled by itself.
• All exams are approximately 60 minutes and will begin promptly at the designated start time.
• You may use a pencil with an eraser. Technically, students can use a blank sheet of paper during the tests for math-related problems. Specific details will be provided during the sample quiz.
• No calculators will be allowed.
• Must show your USC ID card for identification purposes.

*Note: If you do not have a USC ID card yet, you may use your driver’s license or a passport photo page during the identification process.

 

These *EXAM* times listed below are all in US-Pacific/Los Angeles Time Zone

·         EE 450: 10:00 a.m. to 11:30 a.m.

·         EE 457: 1:00 p.m. to 2:30 p.m.

·         EE 477: 3:30 p.m. to 5:00 p.m.

-We no longer offer EE-479 as a placement exam. 

-You will find out your test results (Pass or No Pass) right after completing the exam online. 

-You can also login to http://myviterbi.usc.edu and view your results record a few business days after the exam date.

-Once you have passed the necessary placement tests, you will be able to register for the higher-level course with the corresponding prerequisite for any future semester. Please email your student services advisor to waive the prerequisite for you in the Student Information System.

-Passing a placement exam fulfills or waives a prerequisite for a 500/600-level graduate course, but it does not satisfy graduate credit for a USC degree program.

-Passing a *proficiency exam waives a specific degree requirement in the MSECEM degree, but does not waive the prerequisite for 500/600 level courses requiring it. If you want to take a 500 level course that requires EE 483 after passing the proficiency exam, then you must go back and take EE 483.

-For specific questions about the EE-450, EE-457, and EE-477 placement exam process, please email Patty Rinehart, ECE Student Services Advisor/Associate Director at ptrinida@usc.edu

EE 450: Introduction to Computer Networks

Recommended Textbooks:

Computer Networks by Peterson
Data & Computer Communication by Stallings
Computer Networks by Tannenbaum

Brief Syllabus
Communications networks and services, classifications of networks, performance measures such as Throughput and Delay. The public Internet and PSTN. Convergence of services. Networking topologies.
Network layered architecture, protocols and interfaces. OSI model, TCP/IP model, two- and three-tier client-server models, peer-process communications
Data communications: Analog and digital signaling, sampling theorem, data and signaling rates, modems, time division and statistical multiplexing, link capacity, transmission media, line coding.
Link layer Procedures: Error detection and control, flow control, sliding window procedures. Examples of link protocols including PPP and HDLC.
Local Area Networks: Ethernet, Token rings and wireless LANs. Media access control procedures, CSMA/CD, Token Passing and CSMA/CA. Shared vs. switched LANs. LAN hardware and software components. LAN performance analysis
TCP/IP and the Internet: The Internet Protocol, packet format, IP addressing and subnetting, fragmentation and re-assembly, address resolution protocol, routing and forwarding tables, routing algorithms (RIP, OSPF and BGP), transport layer protocols, TCP and UDP, connection establishment, end-to-end flow and error control procedures, advertised windows, slow-start, long-fat networks, congestion control, port and socket addressing, etc…

Watch online modules of EE-450 concepts below:

EE457: Computer Systems Organization

Textbook: Computer Organization & Design - The Hardware and Software Interface (2nd edition) by D. A. Patterson (Berkeley) and J. L. Hennessey (Stanford)

Brief Syllabus:

EE102L review: Basic digital system design -- Datapath unit design and Control unit design
Basic concepts of assembly language, unsigned and signed numbers, Booth's multiplication and restoring and non-restoring division algorithms.
CPU performance: relation between execution time of a program and the CPU specs (instruction count, clocks per instruction, and clock period).
Compare and contrast CISC and RISC instruction sets, simple ALU design, CLA (carry look-ahead adder), CSA (carry save adder) and application to multiplication.
CPU design: Single cycle CPU design, multi-cycle CPU design, pipelined CPU design including dependencies, hazard detection, stalling, forwarding, branching, flushing, branch penalty due to flushing, branch delay slots.
Memory and cache organization: fully associative, direct, and set associative mappings, cache TAG RAMs, and cache DATA RAMs, interleaved main memory to facilitate fast block transfer between main memory.
Virtual memory: page tables (single-level, multi-level), TLBs, introduction to multiprocessors, cache coherency (MESI protocol).

EE 477: MOS VLSI Circuit Design

Recommended Textbook: Principles of CMOS VLSI Design by Weste and Eshroghian

Course description
Analysis and design of digital MOS VLSI circuits including area, delay and power minimization. Laboratory assignments including design, layout, extraction, simulation and automatic synthesis.
Brief Syllabus

Static characteristics: structure and (V-I) characteristics of MOSFETs, operation as a switch (including weak values), example CMOS and pass transistor circuits, static characteristics of CMOS and pseudo-nMOS inverters.
Layout preliminaries: Introduction to semiconductor processing, layout, and design rules.
Parasitics and performance: Estimation of parasitics from layout, analytical as well as empirical delay models for gates, wires, and pass transistors. Estimation of power dissipation.
Design of complementary CMOS, pass-transistor and dynamic logic circuits.
Design optimizations: Preferred gate types for various logic styles; buffer design for high fan-out, buffering long wires; transistor level optimizations --- body effect, charge sharing, diffusion capacitance minimization, and transistor sizing; custom layout optimization.
Clocking; latch and flip-flop designs, clocking strategies.

Watch online modules of EE-477 concepts below: